ZHCSE07B July 2015 – September 2024 INA226-Q1
PRODUCTION DATA
- 1
- 1 特性
- 2 应用
- 3 说明
- 4 Pin Configuration and Functions
- 5 Specifications
-
6 Detailed Description
- 6.1 Overview
- 6.2 Functional Block Diagram
- 6.3 Feature Description
- 6.4 Device Functional Modes
- 6.5 Programming
-
7 Registers
- 7.1
Register Maps
- 7.1.1 Configuration Register (00h) (Read/Write)
- 7.1.2 Shunt Voltage Register (01h) (Read-Only)
- 7.1.3 Bus Voltage Register (02h) (Read-Only) #GUID-792F23A7-1E45-4FB9-9334-0BF769622DE4/SBOS5477597
- 7.1.4 Power Register (03h) (Read-Only)
- 7.1.5 Current Register (04h) (Read-Only)
- 7.1.6 Calibration Register (05h) (Read/Write)
- 7.1.7 Mask/Enable Register (06h) (Read/Write)
- 7.1.8 Alert Limit Register (07h) (Read/Write)
- 7.1.9 Manufacturer ID Register (FEh) (Read-Only)
- 7.1.10 Die ID Register (FFh) (Read-Only)
- 7.1
Register Maps
- 8 Application and Implementation
- 9 Device and Documentation Support
- 10Revision History
- 11Mechanical, Packaging, and Orderable Information
6.5.5.3.1 High-Speed I2C Mode
When the bus is idle, both the SDA and SCL lines are pulled high by the pullup resistors. The master generates a start condition followed by a valid serial byte containing high-speed (HS) master code 00001XXX. This transmission is made in fast (400 kHz) or standard (100 kHz) (F/S) mode at no more than 400 kHz. The device does not acknowledge the HS master code, but does recognize the code and switches the internal filters to support 2.94 MHz operation.
The master then generates a repeated start condition (a repeated start condition has the same timing as the start condition). After this repeated start condition, the protocol is the same as F/S mode, except that transmission speeds up to 2.94 MHz are allowed. Instead of using a stop condition, use repeated start conditions to secure the bus in HS-mode. A stop condition ends the HS-mode and switches all the internal filters of the device to support the F/S mode.
Figure 6-8 Bus Timing Diagram| PARAMETER | FAST MODE | HIGH-SPEED MODE | UNIT | |||
|---|---|---|---|---|---|---|
| MIN | MAX | MIN | MAX | |||
| SCL operating frequency | f(SCL) | 0.001 | 0.4 | 0.001 | 2.94 | MHz |
| Bus free time between stop and start conditions | t(BUF) | 600 | 160 | ns | ||
| Hold time after repeated START condition. After this period, the first clock is generated. | t(HDSTA) | 100 | 100 | ns | ||
| Repeated start condition setup time | t(SUSTA) | 100 | 100 | ns | ||
| STOP condition setup time | t(SUSTO) | 100 | 100 | ns | ||
| Data hold time | t(HDDAT) | 10 | 900 | 10 | 100 | ns |
| Data setup time | t(SUDAT) | 100 | 20 | ns | ||
| SCL clock low period | t(LOW) | 1300 | 200 | ns | ||
| SCL clock high period | t(HIGH) | 600 | 60 | ns | ||
| Data fall time | tF | 300 | 80 | ns | ||
| Clock fall time | tF | 300 | 40 | ns | ||
| Clock rise time | tR | 300 | 40 | ns | ||
| Clock/data rise time for SCLK ≤ 100kHz | tR | 1000 | ns | |||