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ZHCSL81A May 2020 – June 2021 INA229-Q1

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7.6.1 INA229-Q1 Registers

Table 7-3 lists the INA229-Q1 registers. All register locations not listed in Table 7-3 should be considered as reserved locations and the register contents should not be modified.

Table 7-3 INA229-Q1 Registers

Address	Acronym	Register Name	Register Size (bits)	Section
0h	CONFIG	Configuration	16	Go
1h	ADC_CONFIG	ADC Configuration	16	Go
2h	SHUNT_CAL	Shunt Calibration	16	Go
3h	SHUNT_TEMPCO	Shunt Temperature Coefficient	16	Go
4h	VSHUNT	Shunt Voltage Measurement	24	Go
5h	VBUS	Bus Voltage Measurement	24	Go
6h	DIETEMP	Temperature Measurement	16	Go
7h	CURRENT	Current Result	24	Go
8h	POWER	Power Result	24	Go
9h	ENERGY	Energy Result	40	Go
Ah	CHARGE	Charge Result	40	Go
Bh	DIAG_ALRT	Diagnostic Flags and Alert	16	Go
Ch	SOVL	Shunt Overvoltage Threshold	16	Go
Dh	SUVL	Shunt Undervoltage Threshold	16	Go
Eh	BOVL	Bus Overvoltage Threshold	16	Go
Fh	BUVL	Bus Undervoltage Threshold	16	Go
10h	TEMP_LIMIT	Temperature Over-Limit Threshold	16	Go
11h	PWR_LIMIT	Power Over-Limit Threshold	16	Go
3Eh	MANUFACTURER_ID	Manufacturer ID	16	Go
3Fh	DEVICE_ID	Device ID	16	Go

Complex bit access types are encoded to fit into small table cells. Table 7-4 shows the codes that are used for access types in this section.

Table 7-4 INA229-Q1 Access Type Codes

Access Type	Code	Description
Read Type
R	R	Read
Write Type
W	W	Write
Reset or Default Value
-n		Value after reset or the default value

7.6.1.1 Configuration (CONFIG) Register (Address = 0h) [reset = 0h]

The CONFIG register is shown in Table 7-5.

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Table 7-5 CONFIG Register Field Descriptions

Bit	Field	Type	Reset	Description
15	RST	R/W	0h	Reset Bit. Setting this bit to '1' generates a system reset that is the same as power-on reset. Resets all registers to default values. 0h = Normal Operation 1h = System Reset sets registers to default values This bit self-clears.
14	RSTACC	R/W	0h	Resets the contents of accumulation registers ENERGY and CHARGE to 0 0h = Normal Operation 1h = Clears registers to default values for ENERGY and CHARGE registers
13-6	CONVDLY	R/W	0h	Sets the Delay for initial ADC conversion in steps of 2 ms. 0h = 0 s 1h = 2 ms FFh = 510 ms
5	TEMPCOMP	R/W	0h	Enables temperature compensation of an external shunt 0h = Shunt Temperature Compensation Disabled 1h = Shunt Temperature Compensation Enabled
4	ADCRANGE	R/W	0h	Shunt full scale range selection across IN+ and IN–. 0h = ±163.84 mV 1h = ± 40.96 mV
3-0	RESERVED	R	0h	Reserved. Always reads 0.

7.6.1.2 ADC Configuration (ADC_CONFIG) Register (Address = 1h) [reset = FB68h]

The ADC_CONFIG register is shown in Table 7-6.

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Table 7-6 ADC_CONFIG Register Field Descriptions

Bit	Field	Type	Reset	Description
15-12	MODE	R/W	Fh	The user can set the MODE bits for continuous or triggered mode on bus voltage, shunt voltage or temperature measurement. 0h = Shutdown 1h = Triggered bus voltage, single shot 2h = Triggered shunt voltage, single shot 3h = Triggered shunt voltage and bus voltage, single shot 4h = Triggered temperature, single shot 5h = Triggered temperature and bus voltage, single shot 6h = Triggered temperature and shunt voltage, single shot 7h = Triggered bus voltage, shunt voltage and temperature, single shot 8h = Shutdown 9h = Continuous bus voltage only Ah = Continuous shunt voltage only Bh = Continuous shunt and bus voltage Ch = Continuous temperature only Dh = Continuous bus voltage and temperature Eh = Continuous temperature and shunt voltage Fh = Continuous bus voltage, shunt voltage and temperature
11-9	VBUSCT	R/W	5h	Sets the conversion time of the bus voltage measurement: 0h = 50 µs 1h = 84 µs 2h = 150 µs 3h = 280 µs 4h = 540 µs 5h = 1052 µs 6h = 2074 µs 7h = 4120 µs
8-6	VSHCT	R/W	5h	Sets the conversion time of the shunt voltage measurement: 0h = 50 µs 1h = 84 µs 2h = 150 µs 3h = 280 µs 4h = 540 µs 5h = 1052 µs 6h = 2074 µs 7h = 4120 µs
5-3	VTCT	R/W	5h	Sets the conversion time of the temperature measurement: 0h = 50 µs 1h = 84 µs 2h = 150 µs 3h = 280 µs 4h = 540 µs 5h = 1052 µs 6h = 2074 µs 7h = 4120 µs
2-0	AVG	R/W	0h	Selects ADC sample averaging count. The averaging setting applies to all active inputs. When >0h, the output registers are updated after the averaging has completed. 0h = 1 1h = 4 2h = 16 3h = 64 4h = 128 5h = 256 6h = 512 7h = 1024

7.6.1.3 Shunt Calibration (SHUNT_CAL) Register (Address = 2h) [reset = 1000h]

The SHUNT_CAL register is shown in Table 7-7.

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Table 7-7 SHUNT_CAL Register Field Descriptions

Bit	Field	Type	Reset	Description
15	RESERVED	R	0h	Reserved. Always reads 0.
14-0	SHUNT_CAL	R/W	1000h	The register provides the device with a conversion constant value that represents shunt resistance used to calculate current value in Amperes. This also sets the resolution for the CURRENT register. Value calculation under Section 8.1.2.

7.6.1.4 Shunt Temperature Coefficient (SHUNT_TEMPCO) Register (Address = 3h) [reset = 0h]

The SHUNT_TEMPCO register is shown in Table 7-8.

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Table 7-8 SHUNT_TEMPCO Register Field Descriptions

Bit	Field	Type	Reset	Description
15-14	RESERVED	R	0h	Reserved. Always reads 0.
13-0	TEMPCO	R/W	0h	Temperature coefficient of the shunt for temperature compensation correction. Calculated with respect to +25 °C. The full scale value of the register is 16383 ppm/°C. The 16 bit register provides a resolution of 1ppm/°C/LSB 0h = 0 ppm/°C 3FFFh = 16383 ppm/°C

Bit

Field

Type

Reset

Description

15-14

RESERVED

Reserved. Always reads 0.

13-0

TEMPCO

R/W

Temperature coefficient of the shunt for temperature compensation correction. Calculated with respect to +25 °C.
The full scale value of the register is 16383 ppm/°C.
The 16 bit register provides a resolution of 1ppm/°C/LSB

0h = 0 ppm/°C

3FFFh = 16383 ppm/°C

7.6.1.5 Shunt Voltage Measurement (VSHUNT) Register (Address = 4h) [reset = 0h]

The VSHUNT register is shown in Table 7-9.

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Table 7-9 VSHUNT Register Field Descriptions

Bit	Field	Type	Reset	Description
23-4	VSHUNT	R	0h	Differential voltage measured across the shunt output. Two's complement value. Conversion factor: 312.5 nV/LSB when ADCRANGE = 0 78.125 nV/LSB when ADCRANGE = 1
3-0	RESERVED	R	0h	Reserved. Always reads 0.

7.6.1.6 Bus Voltage Measurement (VBUS) Register (Address = 5h) [reset = 0h]

The VBUS register is shown in Table 7-10.

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Table 7-10 VBUS Register Field Descriptions

Bit	Field	Type	Reset	Description
23-4	VBUS	R	0h	Bus voltage output. Two's complement value, however always positive. Conversion factor: 195.3125 µV/LSB
3-0	RESERVED	R	0h	Reserved. Always reads 0.

7.6.1.7 Temperature Measurement (DIETEMP) Register (Address = 6h) [reset = 0h]

The DIETEMP register is shown in Table 7-11.

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Table 7-11 DIETEMP Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	DIETEMP	R	0h	Internal die temperature measurement. Two's complement value. Conversion factor: 7.8125 m°C/LSB

7.6.1.8 Current Result (CURRENT) Register (Address = 7h) [reset = 0h]

The CURRENT register is shown in Table 7-12.

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Table 7-12 CURRENT Register Field Descriptions

Bit	Field	Type	Reset	Description
23-4	CURRENT	R	0h	Calculated current output in Amperes. Two's complement value. Value description under Section 8.1.2.
3-0	RESERVED	R	0h	Reserved. Always reads 0.

7.6.1.9 Power Result (POWER) Register (Address = 8h) [reset = 0h]

The POWER register is shown in Table 7-13.

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Table 7-13 POWER Register Field Descriptions

Bit	Field	Type	Reset	Description
23-0	POWER	R	0h	Calculated power output. Output value in watts. Unsigned representation. Positive value. Value description under Section 8.1.2.

7.6.1.10 Energy Result (ENERGY) Register (Address = 9h) [reset = 0h]

The ENERGY register is shown in Table 7-14.

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Table 7-14 ENERGY Register Field Descriptions

Bit	Field	Type	Reset	Description
39-0	ENERGY	R	0h	Calculated energy output. Output value is in Joules.Unsigned representation. Positive value. Value description under Section 8.1.2.

7.6.1.11 Charge Result (CHARGE) Register (Address = Ah) [reset = 0h]

The CHARGE register is shown in Table 7-15.

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Table 7-15 CHARGE Register Field Descriptions

Bit	Field	Type	Reset	Description
39-0	CHARGE	R	0h	Calculated charge output. Output value is in Coulombs.Two's complement value. Value description under Section 8.1.2.

7.6.1.12 Diagnostic Flags and Alert (DIAG_ALRT) Register (Address = Bh) [reset = 0001h]

The DIAG_ALRT register is shown in Table 7-16.

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Table 7-16 DIAG_ALRT Register Field Descriptions

Bit	Field	Type	Reset	Description
15	ALATCH	R/W	0h	When the Alert Latch Enable bit is set to Transparent mode, the Alert pin and Flag bit reset to the idle state when the fault has been cleared. When the Alert Latch Enable bit is set to Latch mode, the Alert pin and Alert Flag bit remain active following a fault until the DIAG_ALRT Register has been read. 0h = Transparent 1h = Latched
14	CNVR	R/W	0h	Setting this bit high configures the Alert pin to be asserted when the Conversion Ready Flag (bit 1) is asserted, indicating that a conversion cycle has completed. 0h = Disable conversion ready flag on ALERT pin 1h = Enables conversion ready flag on ALERT pin
13	SLOWALERT	R/W	0h	When enabled, ALERT function is asserted on the completed averaged value. This gives the flexibility to delay the ALERT until after the averaged value. 0h = ALERT comparison on non-averaged (ADC) value 1h = ALERT comparison on averaged value
12	APOL	R/W	0h	Alert Polarity bit sets the Alert pin polarity. 0h = Normal (Active-low, open-drain) 1h = Inverted (active-high, open-drain )
11	ENERGYOF	R	0h	This bit indicates the health of the ENERGY register. If the 40 bit ENERGY register has overflowed this bit is set to 1. 0h = Normal 1h = Overflow Clears when the ENERGY register is read.
10	CHARGEOF	R	0h	This bit indicates the health of the CHARGE register. If the 40 bit CHARGE register has overflowed this bit is set to 1. 0h = Normal 1h = Overflow Clears when the CHARGE register is read.
9	MATHOF	R	0h	This bit is set to 1 if an arithmetic operation resulted in an overflow error. It indicates that current and power data may be invalid. 0h = Normal 1h = Overflow Must be manually cleared by triggering another conversion or by clearing the accumulators with the RSTACC bit.
8	RESERVED	R	0h	Reserved. Always read 0.
7	TMPOL	R/W	0h	This bit is set to 1 if the temperature measurement exceeds the threshold limit in the temperature over-limit register. 0h = Normal 1h = Over Temp Event When ALATCH =1 this bit is cleared by reading this register.
6	SHNTOL	R/W	0h	This bit is set to 1 if the shunt voltage measurement exceeds the threshold limit in the shunt over-limit register. 0h = Normal 1h = Over Shunt Voltage Event When ALATCH =1 this bit is cleared by reading this register.
5	SHNTUL	R/W	0h	This bit is set to 1 if the shunt voltage measurement falls below the threshold limit in the shunt under-limit register. 0h = Normal 1h = Under Shunt Voltage Event When ALATCH =1 this bit is cleared by reading this register.
4	BUSOL	R/W	0h	This bit is set to 1 if the bus voltage measurement exceeds the threshold limit in the bus over-limit register. 0h = Normal 1h = Bus Over-Limit Event When ALATCH =1 this bit is cleared by reading this register.
3	BUSUL	R/W	0h	This bit is set to 1 if the bus voltage measurement falls below the threshold limit in the bus under-limit register. 0h = Normal 1h = Bus Under-Limit Event When ALATCH =1 this bit is cleared by reading this register.
2	POL	R/W	0h	This bit is set to 1 if the power measurement exceeds the threshold limit in the power limit register. 0h = Normal 1h = Power Over-Limit Event When ALATCH =1 this bit is cleared by reading this register.
1	CNVRF	R/W	0h	This bit is set to 1 if the conversion is completed. 0h = Normal 1h = Conversion is complete When ALATCH =1 this bit is cleared by reading this register or starting a new triggered conversion.
0	MEMSTAT	R/W	1h	This bit is set to 0 if a checksum error is detected in the device trim memory space. 0h = Memory Checksum Error 1h = Normal Operation

7.6.1.13 Shunt Overvoltage Threshold (SOVL) Register (Address = Ch) [reset = 7FFFh]

If negative values are entered in this register, then a shunt voltage measurement of 0 V will trip this alarm. When using negative values for the shunt under and overvoltage thresholds be aware that the over voltage threshold must be set to the larger (that is, less negative) of the two values. The SOVL register is shown in Table 7-17.

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Table 7-17 SOVL Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	SOVL	R/W	7FFFh	Sets the threshold for comparison of the value to detect Shunt Overvoltage (overcurrent protection). Two's complement value. Conversion Factor: 5 µV/LSB when ADCRANGE = 0 1.25 µV/LSB when ADCRANGE = 1.

7.6.1.14 Shunt Undervoltage Threshold (SUVL) Register (Address = Dh) [reset = 8000h]

The SUVL register is shown in Table 7-18.

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Table 7-18 SUVL Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	SUVL	R/W	8000h	Sets the threshold for comparison of the value to detect Shunt Undervoltage (undercurrent protection). Two's complement value. Conversion Factor: 5 µV/LSB when ADCRANGE = 0 1.25 µV/LSB when ADCRANGE = 1.

7.6.1.15 Bus Overvoltage Threshold (BOVL) Register (Address = Eh) [reset = 7FFFh]

The BOVL register is shown in Table 7-19.

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Table 7-19 BOVL Register Field Descriptions

Bit	Field	Type	Reset	Description
15	Reserved	R	0h	Reserved. Always reads 0.
14-0	BOVL	R/W	7FFFh	Sets the threshold for comparison of the value to detect Bus Overvoltage (overvoltage protection). Unsigned representation, positive value only. Conversion factor: 3.125 mV/LSB.

7.6.1.16 Bus Undervoltage Threshold (BUVL) Register (Address = Fh) [reset = 0h]

The BUVL register is shown in Table 7-20.

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Table 7-20 BUVL Register Field Descriptions

Bit	Field	Type	Reset	Description
15	Reserved	R	0h	Reserved. Always reads 0.
14-0	BUVL	R/W	0h	Sets the threshold for comparison of the value to detect Bus Undervoltage (undervoltage protection). Unsigned representation, positive value only. Conversion factor: 3.125 mV/LSB.

7.6.1.17 Temperature Over-Limit Threshold (TEMP_LIMIT) Register (Address = 10h) [reset = 7FFFh]

The TEMP_LIMIT register is shown in Table 7-21.

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Table 7-21 TEMP_LIMIT Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	TOL	R/W	7FFFh	Sets the threshold for comparison of the value to detect over temperature measurements. Two's complement value. The value entered in this field compares directly against the value from the DIETEMP register to determine if an over temperature condition exists. Conversion factor: 7.8125 m°C/LSB.

7.6.1.18 Power Over-Limit Threshold (PWR_LIMIT) Register (Address = 11h) [reset = FFFFh]

The PWR_LIMIT register is shown in Table 7-22.

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Table 7-22 PWR_LIMIT Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	POL	R/W	FFFFh	Sets the threshold for comparison of the value to detect power over-limit measurements. Unsigned representation, positive value only. The value entered in this field compares directly against the value from the POWER register to determine if an over power condition exists. Conversion factor: 256 × Power LSB.

7.6.1.19 Manufacturer ID (MANUFACTURER_ID) Register (Address = 3Eh) [reset = 5449h]

The MANUFACTURER_ID register is shown in Table 7-23.

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Table 7-23 MANUFACTURER_ID Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	MANFID	R	5449h	Reads back TI in ASCII.

7.6.1.20 Device ID (DEVICE_ID) Register (Address = 3Fh) [reset = 2291h]

The DEVICE_ID register is shown in Table 7-24.

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Table 7-24 DEVICE_ID Register Field Descriptions

Bit	Field	Type	Reset	Description
15-4	DIEID	R	229h	Stores the device identification bits.
3-0	REV_ID	R	1h	Device revision identification.