The primary communication between the INA229-Q1 and the external MCU is through the SPI bus, which provides full-duplex communications in a main-secondary configuration. The external MCU is always the primary or main SPI device, sending command requests on the MOSI pin, and receiving device responses on the MISO pin. The INA229-Q1 is always an SPI secondary device, receiving command requests and sending responses (status, measured values) to the external MCU over the MISO pin.

• SPI is a 4-pin interface with pins as:
  • CS - SPI Chip Select (input)
  • SCLK - SPI Clock (input)
  • MOSI - SPI Secondary In / Main Out data (input)
  • MISO - SPI Secondary Out / Main In data (tri-state output)
• The SPI frame size is variable in length depending on the INA229-Q1 register accessed through the SPI interface as following:
  • Main to Secondary (MOSI): 6 bits for register Address; 1 bit low; 1 R/W bit (read / not write); variable length of low bits depending on the INA229-Q1 register length.
  • Secondary to Main (MISO): 8 bits low; variable length of bits depending on the INA229-Q1 register length.
• SPI bit-speed up to 10 Mbit/s
• Both Main commands and INA229-Q1 data are shifted MSB first, LSB last
• The data on the MOSI line is sampled on the falling edge of SCLK
• The data on the MISO line is shifted out on the rising edge of SCLK

The SPI communication starts with the CS falling edge, and ends with CS rising edge. The CS high level keeps secondary SPI interface in an idle state, and MISO output is tri-stated.

Since the MISO output is push-pull it is ideal to have the INA229-Q1 supply at the same voltage as the primary device I/O supply. If different supply voltages are used, level translation is recommended.