SPI communication to the INA229-Q1 device is performed through register address access. Communication to every register starts with a 6-bit register address followed by a "0" and a R/W bit. Setting the R/W bit to "1" indicates that the current SPI frame will read from a device register while setting the R/W bit to "0" indicates the current SPI frame will write data to a device register.

Figure 7-7 SPI Read Frame

Figure 7-8 SPI Write Frame

Note that while the read frame can be variable in length due to the different length registers in the INA229-Q1 device, the write frame is fixed in length as all writable registers are 16 bits wide. During an SPI write frame, while new data is shifted into the INA229-Q1 register, the old data from the same register is shifted out on the MISO line.

The first 8-bits of each SPI frame are presented in Table 7-2, which shows access to a certain register address on the MOSI line as well as read/write functionality. On an SPI read operation, the INA229-Q1 returns the data read in the same SPI frame.