ZHCSL81A May   2020  – June 2021 INA229-Q1

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements (SPI)
    7. 6.7 Timing Diagram
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Versatile High Voltage Measurement Capability
      2. 7.3.2 Internal Measurement and Calculation Engine
      3. 7.3.3 Low Bias Current
      4. 7.3.4 High-Precision Delta-Sigma ADC
        1. 7.3.4.1 Low Latency Digital Filter
        2. 7.3.4.2 Flexible Conversion Times and Averaging
      5. 7.3.5 Shunt Resistor Drift Compensation
      6. 7.3.6 Integrated Precision Oscillator
      7. 7.3.7 Multi-Alert Monitoring and Fault Detection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown Mode
      2. 7.4.2 Power-On Reset
    5. 7.5 Programming
      1. 7.5.1 Serial Interface
        1. 7.5.1.1 SPI Frame
    6. 7.6 Register Maps
      1. 7.6.1 INA229-Q1 Registers
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Device Measurement Range and Resolution
      2. 8.1.2 Current , Power, Energy, and Charge Calculations
      3. 8.1.3 ADC Output Data Rate and Noise Performance
      4. 8.1.4 Input Filtering Considerations
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Select the Shunt Resistor
        2. 8.2.2.2 Configure the Device
        3. 8.2.2.3 Program the Shunt Calibration Register
        4. 8.2.2.4 Set Desired Fault Thresholds
        5. 8.2.2.5 Calculate Returned Values
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 接收文档更新通知
    2. 11.2 支持资源
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 术语表
  12. 12Mechanical, Packaging, and Orderable Information

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机械数据 (封装 | 引脚)
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6.6 Timing Requirements (SPI)

MIN NOM MAX UNIT
SERIAL INTERFACE
fSPI SPI bit frequency 10 MHz
tSCLK_H SCLK high time 40 ns
tSCLK_L SCLK low time 40 ns
tCSF_SCLKR CS fall to first SCLK rise time 10 ns
tSCLKF_CSR Last SCLK fall to CS rise time 10 ns
tFRM_DLY Sequential transfer delay (1) 50 ns
tMOSI_RF MOSI Rise and Fall time, 10 MHz SCLK 15 ns
tMOSI_ST MOSI data setup time 10 ns
tMOSI_HLD MOSI data hold time 20 ns
tMISO_RF MISO Rise and Fall time, CLOAD = 200 pF 15 ns
tMISO_ST MISO data setup time 20 ns
tMISO_HLD MISO data hold time 20 ns
tCS_MISO_DLY CS falling edge to MISO data valid delay time 25 ns
tCS_MISO_HIZ CS rising edge to MISO high impedance delay time 25 ns
(1) Optional. The SPI interface can operate without the CS pin assistance as long as the pin is held low.
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