ZHCS766A February 2012 – December 2021 INA230
PRODUCTION DATA
To communicate with the INA230, the controller must first address target devices using a corresponding target address byte. The target address byte consists of seven address bits and a direction bit that indicates whether the action is to be a read or write operation.
The INA230 has two address pins: A0 and A1. Table 8-2 describes the pin logic levels for each of the 16 possible addresses. The state of pins A0 and A1 is sampled on every bus communication and should be set before any activity on the interface occurs.
A1 | A0 | TARGET ADDRESS |
---|---|---|
GND | GND | 1000000 |
GND | VS | 1000001 |
GND | SDA | 1000010 |
GND | SCL | 1000011 |
VS | GND | 1000100 |
VS | VS | 1000101 |
VS | SDA | 1000110 |
VS | SCL | 1000111 |
SDA | GND | 1001000 |
SDA | VS | 1001001 |
SDA | SDA | 1001010 |
SDA | SCL | 1001011 |
SCL | GND | 1001100 |
SCL | VS | 1001101 |
SCL | SDA | 1001110 |
SCL | SCL | 1001111 |