ZHCS766A February 2012 – December 2021 INA230
PRODUCTION DATA
| MIN | NOM | MAX | UNIT | ||
|---|---|---|---|---|---|
| I2C BUS (FAST MODE) | |||||
| F(SCL) | I2C clock frequency | 1 | 400 | kHz | |
| t(BUF) | Bus free time between STOP and START conditions | 600 | ns | ||
| t(HDSTA) | Hold time after a repeated START condition. After this period, the first clock is generated. | 100 | ns | ||
| t(SUSTA) | Repeated START condition setup time | 100 | ns | ||
| t(SUSTO) | STOP condition setup time | 100 | ns | ||
| t(HDDAT) | Data hold time | 0 | ns | ||
| t(SUDAT) | Data setup time | 100 | ns | ||
| t(LOW) | SCL clock low period | 1300 | ns | ||
| t(HIGH) | SCL clock high period | 600 | ns | ||
| tF | Clock/data fall time | 300 | ns | ||
| tR | Clock/data rise time | 300 | ns | ||
| tR | Clock rise time (SCLK ≤ 100 kHz) | 1000 | ns | ||
| I2C BUS (HIGH-SPEED MODE) | |||||
| F(SCL) | I2C clock frequency | 10 | 3400 | kHz | |
| t(BUF) | Bus free time between STOP and START conditions | 160 | ns | ||
| t(HDSTA) | Hold time after a repeated START condition. After this period, the first clock is generated. | 100 | ns | ||
| t(SUSTA) | Repeated START condition setup time | 100 | ns | ||
| t(SUSTO) | STOP condition setup time | 100 | ns | ||
| t(HDDAT) | Data hold time | 0 | ns | ||
| t(SUDAT) | Data setup time | 10 | ns | ||
| t(LOW) | SCL clock low period | 160 | ns | ||
| t(HIGH) | SCL clock high period | 60 | ns | ||
| tF | Clock/data fall time | 160 | ns | ||
| tR | Clock/data rise time | 160 | ns | ||