The INA231 offers compatibility with both I²C and SMBus interfaces. The I²C and SMBus protocols are essentially compatible with one another.

The I²C interface is used throughout this data sheet as the primary example, with SMBus protocol specified only when a difference between the two systems is discussed. Two bidirectional lines, SCL and SDA, connect the INA231 to the bus. Both SCL and SDA are open-drain connections.

The device that initiates a data transfer is called a master, and the devices controlled by the master are slaves. The bus must be controlled by a master device that generates the serial clock (SCL), controls the bus access, and generates start and stop conditions.

To address a specific device, the master initiates a start condition by pulling the data signal line (SDA) from a high to a low logic level while SCL is high. All slaves on the bus shift in the slave address byte on the rising edge of SCL, with the last bit indicating whether a read or write operation is intended. During the ninth clock pulse, the slave being addressed responds to the master by generating an Acknowledge bit (ACK) and pulling SDA low.

Data transfer is then initiated and eight bits of data are sent, followed by an ACK. During data transfer, SDA must remain stable while SCL is high. Any change in SDA while SCL is high is interpreted as a start or stop condition.

After all data have been transferred, the master generates a stop condition indicated by pulling SDA from low to high while SCL is high. The INA231 includes a 28-ms timeout on its interface to prevent locking up the bus.

Accessing a specific register on the INA231 is accomplished by writing the appropriate value to the register pointer. Refer to Table 8-3 for a complete list of registers and corresponding addresses. The value for the register pointer (shown in Figure 8-7) is the first byte transferred after the slave address byte with the R/ W bit low. Every write operation to the INA231 requires a value for the register pointer.

Writing to a register begins with the first byte transmitted by the master. This byte is the slave address, with the R/ W bit low. The INA231 then acknowledges receipt of a valid address. The next byte transmitted by the master is the address of the register that data are written to. This register address value updates the register pointer to the desired register. The next two bytes are written to the register addressed by the register pointer. The INA231 acknowledges receipt of each data byte. The master may terminate data transfer by generating a start or stop condition.

When reading from the INA231, the last value stored in the register pointer by a write operation determines which register is read during a read operation. To change the register pointer for a read operation, a new value must be written to the register pointer. This write is accomplished by issuing a slave address byte with the R/ W bit low, followed by the register pointer byte. No additional data are required. The master then generates a start condition and sends the slave address byte with the R/ W bit high to initiate the read command. The next byte is transmitted by the slave and is the most significant byte of the register indicated by the register pointer. This byte is followed by an ACK from the master; then the slave transmits the least significant byte. The master acknowledges receipt of the data byte. The master may terminate data transfer by generating a Not-Acknowledge bit (No ACK) after receiving any data byte, or generating a start or stop condition. If repeated reads from the same register are desired, it is not necessary to continually send the register pointer bytes; the INA231 retains the register pointer value until it is changed by the next write operation.

Figure 8-4 and Figure 8-5 show the write and read operation timing diagrams, respectively. Note that register bytes are sent most-significant byte first, followed by the least significant byte.

A. The value of the slave address byte is determined by the settings of the A0 and A1 pins. Refer to Table 8-2.

Figure 8-4 Timing Diagram for Write Word Format

A. The value of the slave address byte is determined by the settings of the A0 and A1 pins. Refer to Table 8-2.

B. Read data are from the last register pointer location. If a new register is desired, the register pointer must be updated. See Figure 8-7.

C. ACK by Master can also be sent.

Figure 8-5 Timing Diagram for Read Word Format

Figure 8-6 shows the timing diagram for the SMBus alert response operation. Figure 8-7 illustrates a typical register pointer configuration.

A. The slave address byte value is determined by the settings of the A0 and A1 pins. Refer to Table 8-2.

Figure 8-6 Timing Diagram for SMBus Alert

A. The slave address byte value is determined by the settings of the A0 and A1 pins. Refer to Table 8-2.

Figure 8-7 Typical Register Pointer Set