ZHCSLF9A June 2020 – June 2021 INA237-Q1
PRODUCTION DATA
Table 7-3 lists the INA237-Q1 registers. All register locations not listed in Table 7-3 should be considered as reserved locations and the register contents should not be modified.
Address | Acronym | Register Name | Register Size (bits) | Section |
|---|---|---|---|---|
| 0h | CONFIG | Configuration | 16 | Go |
| 1h | ADC_CONFIG | ADC Configuration | 16 | Go |
| 2h | SHUNT_CAL | Shunt Calibration | 16 | Go |
| 4h | VSHUNT | Shunt Voltage Measurement | 16 | Go |
| 5h | VBUS | Bus Voltage Measurement | 16 | Go |
| 6h | DIETEMP | Temperature Measurement | 16 | Go |
| 7h | CURRENT | Current Result | 16 | Go |
| 8h | POWER | Power Result | 24 | Go |
| Bh | DIAG_ALRT | Diagnostic Flags and Alert | 16 | Go |
| Ch | SOVL | Shunt Overvoltage Threshold | 16 | Go |
| Dh | SUVL | Shunt Undervoltage Threshold | 16 | Go |
| Eh | BOVL | Bus Overvoltage Threshold | 16 | Go |
| Fh | BUVL | Bus Undervoltage Threshold | 16 | Go |
| 10h | TEMP_LIMIT | Temperature Over-Limit Threshold | 16 | Go |
| 11h | PWR_LIMIT | Power Over-Limit Threshold | 16 | Go |
| 3Eh | MANUFACTURER_ID | Manufacturer ID | 16 | Go |
Complex bit access types are encoded to fit into small table cells. Table 7-4 shows the codes that are used for access types in this section.
| Access Type | Code | Description |
|---|---|---|
| Read Type | ||
| R | R | Read |
| Write Type | ||
| W | W | Write |
| Reset or Default Value | ||
| -n | Value after reset or the default value | |
The CONFIG register is shown in Table 7-5.
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| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15 | RST | R/W | 0h | Reset Bit. Setting this bit to '1' generates a system reset that is the same as power-on reset. Resets all registers to default values. 0h = Normal Operation 1h = System Reset sets registers to default values This bit self-clears. |
| 14 | RESERVED | R/W | 0h | Reserved. Always reads 0. |
| 13-6 | CONVDLY | R/W | 0h | Sets the Delay for initial ADC conversion in steps of 2 ms. 0h = 0 s 1h = 2 ms FFh = 510 ms |
| 5 | RESERVED | R/W | 0h | Reserved. Always reads 0. |
| 4 | ADCRANGE | R/W | 0h | Shunt full scale range selection across IN+ and IN–. 0h = ±163.84 mV 1h = ± 40.96 mV |
| 3-0 | RESERVED | R | 0h | Reserved. Always reads 0. |
The ADC_CONFIG register is shown in Table 7-6.
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| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-12 | MODE | R/W | Fh | The user can set the MODE bits for continuous or triggered mode on bus voltage,
shunt voltage or temperature measurement. 0h = Shutdown 1h = Triggered bus voltage, single shot 2h = Triggered shunt voltage, single shot 3h = Triggered shunt voltage and bus voltage, single shot 4h = Triggered temperature, single shot 5h = Triggered temperature and bus voltage, single shot 6h = Triggered temperature and shunt voltage, single shot 7h = Triggered bus voltage, shunt voltage and temperature, single shot 8h = Shutdown 9h = Continuous bus voltage only Ah = Continuous shunt voltage only Bh = Continuous shunt and bus voltage Ch = Continuous temperature only Dh = Continuous bus voltage and temperature Eh = Continuous temperature and shunt voltage Fh = Continuous bus voltage, shunt voltage and temperature |
| 11-9 | VBUSCT | R/W | 5h | Sets the conversion time of the bus voltage measurement: 0h = 50 µs 1h = 84 µs 2h = 150 µs 3h = 280 µs 4h = 540 µs 5h = 1052 µs 6h = 2074 µs 7h = 4120 µs |
| 8-6 | VSHCT | R/W | 5h | Sets the conversion time of the shunt voltage measurement: 0h = 50 µs 1h = 84 µs 2h = 150 µs 3h = 280 µs 4h = 540 µs 5h = 1052 µs 6h = 2074 µs 7h = 4120 µs |
| 5-3 | VTCT | R/W | 5h | Sets the conversion time of the temperature measurement: 0h = 50 µs 1h = 84 µs 2h = 150 µs 3h = 280 µs 4h = 540 µs 5h = 1052 µs 6h = 2074 µs 7h = 4120 µs |
| 2-0 | AVG | R/W | 0h | Selects ADC sample averaging count. The averaging setting applies to all active inputs. When >0h, the output registers are updated after the averaging has completed. 0h = 1 1h = 4 2h = 16 3h = 64 4h = 128 5h = 256 6h = 512 7h = 1024 |
The SHUNT_CAL register is shown in Table 7-7.
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| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15 | RESERVED | R | 0h | Reserved. Always reads 0. |
| 14-0 | SHUNT_CAL | R/W | 1000h | The register provides the device with a conversion constant value that represents shunt resistance used to calculate current value in Amperes. This also sets the resolution for the CURRENT register. Value calculation under Section 8.1.2. |
The VSHUNT register is shown in Table 7-8.
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The VBUS register is shown in Table 7-9.
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| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-0 | VBUS | R | 0h | Bus voltage output. Two's complement value, however always positive. Conversion factor: 3.125 mV/LSB |
The DIETEMP register is shown in Table 7-10.
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| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-4 | DIETEMP | R | 0h | Internal die temperature measurement. Two's complement value. Conversion factor: 125 m°C/LSB |
| 3-0 | RESERVED | R | 0h | Reserved. Always reads 0. |
The CURRENT register is shown in Table 7-11.
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| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-0 | CURRENT | R | 0h | Calculated current output in Amperes. Two's complement value. Value description under Section 8.1.2. |
The POWER register is shown in Table 7-12.
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| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 23-0 | POWER | R | 0h | Calculated power output. Output value in watts. Unsigned representation. Positive value. Value description under Section 8.1.2. |
The DIAG_ALRT register is shown in Table 7-13.
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| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15 | ALATCH | R/W | 0h | When the Alert Latch Enable bit is set to Transparent mode, the Alert pin and Flag bit reset to the idle state when the fault has been cleared. When the Alert Latch Enable bit is set to Latch mode, the Alert pin and Alert Flag bit remain active following a fault until the DIAG_ALRT Register has been read. 0h = Transparent 1h = Latched |
| 14 | CNVR | R/W | 0h | Setting this bit high configures the Alert pin to be asserted when the Conversion Ready Flag (bit 1) is asserted, indicating that a conversion cycle has completed. 0h = Disable conversion ready flag on ALERT pin 1h = Enables conversion ready flag on ALERT pin |
| 13 | SLOWALERT | R/W | 0h | When enabled, ALERT function is asserted on the completed averaged value. This gives the flexibility to delay the ALERT until after the averaged value. 0h = ALERT comparison on non-averaged (ADC) value 1h = ALERT comparison on averaged value |
| 12 | APOL | R/W | 0h | Alert Polarity bit sets the Alert pin polarity. 0h = Normal (Active-low, open-drain) 1h = Inverted (active-high, open-drain ) |
| 11-10 | RESERVED | R | 0h | Reserved. Always read 0. |
| 9 | MATHOF | R | 0h | This bit is set to 1 if an arithmetic operation resulted in an overflow error. It indicates that current and power data may be invalid. 0h = Normal 1h = Overflow Must be manually cleared by triggering another conversion. |
| 8 | RESERVED | R | 0h | Reserved. Always read 0. |
| 7 | TMPOL | R/W | 0h | This bit is set to 1 if the temperature measurement exceeds the threshold limit in
the temperature over-limit register. 0h = Normal 1h = Over Temp Event When ALATCH =1 this bit is cleared by reading this register. |
| 6 | SHNTOL | R/W | 0h | This bit is set to 1 if the shunt voltage measurement exceeds the threshold limit
in the shunt over-limit register. 0h = Normal 1h = Over Shunt Voltage Event When ALATCH =1 this bit is cleared by reading this register. |
| 5 | SHNTUL | R/W | 0h | This bit is set to 1 if the shunt voltage measurement falls below the threshold
limit in the shunt under-limit register. 0h = Normal 1h = Under Shunt Voltage Event When ALATCH =1 this bit is cleared by reading this register. |
| 4 | BUSOL | R/W | 0h | This bit is set to 1 if the bus voltage measurement exceeds the threshold limit in
the bus over-limit register. 0h = Normal 1h = Bus Over-Limit Event When ALATCH =1 this bit is cleared by reading this register. |
| 3 | BUSUL | R/W | 0h | This bit is set to 1 if the bus voltage measurement falls below the threshold
limit in the bus under-limit register. 0h = Normal 1h = Bus Under-Limit Event When ALATCH =1 this bit is cleared by reading this register. |
| 2 | POL | R/W | 0h | This bit is set to 1 if the power measurement exceeds the threshold limit in the
power limit register. 0h = Normal 1h = Power Over-Limit Event When ALATCH =1 this bit is cleared by reading this register. |
| 1 | CNVRF | R/W | 0h | This bit is set to 1 if the conversion is completed. 0h = Normal 1h = Conversion is complete When ALATCH =1 this bit is cleared by reading this register or starting a new triggered conversion. |
| 0 | MEMSTAT | R/W | 1h | This bit is set to 0 if a checksum error is detected in the device trim memory space. 0h = Memory Checksum Error 1h = Normal Operation |
If negative values are entered in this register, then a shunt voltage measurement of 0 V will trip this alarm. When using negative values for the shunt under and overvoltage thresholds be aware that the over voltage threshold must be set to the larger (that is, less negative) of the two values. The SOVL register is shown in Table 7-14.
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The SUVL register is shown in Table 7-15.
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The BOVL register is shown in Table 7-16.
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| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15 | Reserved | R | 0h | Reserved. Always reads 0. |
| 14-0 | BOVL | R/W | 7FFFh | Sets the threshold for comparison of the value to detect Bus Overvoltage (overvoltage protection). Unsigned representation, positive value only. Conversion factor: 3.125 mV/LSB. |
The BUVL register is shown in Table 7-17.
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| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15 | Reserved | R | 0h | Reserved. Always reads 0. |
| 14-0 | BUVL | R/W | 0h | Sets the threshold for comparison of the value to detect Bus Undervoltage (undervoltage protection). Unsigned representation, positive value only. Conversion factor: 3.125 mV/LSB. |
The TEMP_LIMIT register is shown in Table 7-18.
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| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-4 | TOL | R/W | 7FFh | Sets the threshold for comparison of the value to detect over temperature measurements. Two's complement value. The value entered in this field compares directly against the value from the DIETEMP register to determine if an over temperature condition exists. Conversion factor: 125 m°C/LSB. |
| 3-0 | Reserved | R | 0 | Reserved, always reads 0 |
The PWR_LIMIT register is shown in Table 7-19.
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| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-0 | POL | R/W | FFFFh | Sets the threshold for comparison of the value to detect power over-limit measurements. Unsigned representation, positive value only. The value entered in this field compares directly against the value from the POWER register to determine if an over power condition exists. Conversion factor: 256 × Power LSB. |
The MANUFACTURER_ID register is shown in Table 7-20.
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| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-0 | MANFID | R | 5449h | Reads back TI in ASCII. |