ZHCSFO8C July   2016  – September 2023 INA250-Q1

PRODUCTION DATA  

  1.   1
  2. 特性
  3. 应用
  4. 说明
  5. Revision History
  6. Pin Configuration and Functions
  7. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Integrated Shunt Resistor
      2. 7.3.2 Short-Circuit Duration
      3. 7.3.3 Temperature Stability
    4. 7.4 Device Functional Modes
      1. 7.4.1 Amplifier Operation
      2. 7.4.2 Input Filtering
        1. 7.4.2.1 Calculating Gain Error Resulting from External Filter Resistance
      3. 7.4.3 Shutting Down the Device
      4. 7.4.4 Using the Device with Common-Mode Transients Above 36 V
  9. Applications and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Current Summing
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curve
      2. 8.2.2 Parallel Multiple INA250-Q1 Devices for Higher Current
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
        3. 8.2.2.3 Application Curve
      3. 8.2.3 Current Differencing
        1. 8.2.3.1 Design Requirements
        2. 8.2.3.2 Detailed Design Procedure
        3. 8.2.3.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Examples
  10. Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 接收文档更新通知
    3. 9.3 支持资源
    4. 9.4 Trademarks
    5. 9.5 静电放电警告
    6. 9.6 术语表
  11. 10Mechanical, Packaging, and Orderable Information

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Calculating Gain Error Resulting from External Filter Resistance

If additional external series filter resistors are added to the circuit, the mismatch in bias currents results in a mismatch of voltage drops across the filter resistors. This mismatch creates a differential error voltage that subtracts from the voltage developed across the Kelvin connection of the shunt resistor, thus reducing the voltage that reaches the amplifier input terminals. Without the additional series resistance, the mismatch in input bias currents has little effect on device operation as a result of the low input bias current of the amplifier and the typically low impedance of the traces between the shunt and amplifier input pins. The amount of error these external filter resistors add to the measurement may be calculated using Equation 3, where the gain error factor is calculated using Equation 2.

The amount of variance between the differential voltage present at the device input relative to the voltage developed at the shunt resistor is based both on the external series resistance value as well as the internal input resistors, RINT, as shown in Figure 7-4. The reduction of the shunt voltage reaching the device input pins appears as a gain error when comparing the output voltage relative to the voltage across the shunt resistor. A factor may be calculated to determine the amount of gain error that is introduced by the addition of external series resistance. Equation 2 calculates the expected deviation from the shunt voltage compared to the expected voltage at the device input pins.

Equation 2. GUID-1986C9B8-651D-40A4-AE4E-77CC2FD5F319-low.gif

where:

  • RINT is the internal input resistor and
  • RS is the external series resistance



Equation 3. GUID-0A092707-4731-4945-B32C-94C91EBFA501-low.gif

With the adjustment factor equation including the device internal input resistance, this factor varies with each gain version, as shown in Table 7-1. Table 7-2 lists the gain error factor for each individual device.

Equation 3 calculates the expected gain error from the addition of the external series resistors.

Table 7-1 Input Resistance
DEVICEGAINRINT
INA250A1-Q1200 mV/A50 kΩ
INA250A2-Q1500 mV/A20 kΩ
INA250A3-Q1800 mV/A12.5 kΩ
INA250A4-Q12 V/A5 kΩ
Table 7-2 Device Gain Error Factor
DEVICESIMPLIFIED GAIN ERROR FACTOR
INA250A1-Q1GUID-90DD90ED-FA28-416E-B796-5E1D3030F3C6-low.gif
INA250A2-Q1GUID-FF7C917E-EBBE-42AF-AA81-70A23D556A84-low.gif
INA250A3-Q1GUID-F9BFF610-B752-4606-BDB5-2AF1526C7AEA-low.gif
INA250A4-Q1GUID-EEF48E69-8BEC-4FF7-A7B5-4D12631576D6-low.gif

For example, using an INA250A2-Q1 device and the corresponding gain error equation from Table 7-2, a series resistance of 10-Ω results in a gain error factor of 0.991. The corresponding gain error is then calculated using Equation 3, resulting in a gain error of approximately 0.84% because of the external 10-Ω series resistors.