ZHCSKF9A October   2019  – November 2020 INA290-Q1

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Amplifier Input Common-Mode Range
        1. 7.3.1.1 Input-Signal Bandwidth
        2. 7.3.1.2 Low Input Bias Current
        3. 7.3.1.3 Low VSENSE Operation
        4. 7.3.1.4 Wide Fixed Gain Output
        5. 7.3.1.5 Wide Supply Range
    4. 7.4 Device Functional Modes
      1. 7.4.1 Unidirectional Operation
      2. 7.4.2 High Signal Throughput
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 RSENSE and Device Gain Selection
      2. 8.1.2 Input Filtering
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Overload Recovery With Negative VSENSE
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 接收文档更新通知
    3. 11.3 支持资源
    4. 11.4 Trademarks
    5. 11.5 静电放电警告
    6. 11.6 术语表
  12. 12Mechanical, Packaging, and Orderable Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

6.5 Electrical Characteristics

at TA = 25 °C, VS = 5 V, VSENSE = VIN+ – VIN– = 0.5 V / Gain, VCM = VIN– = 48 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INPUT
CMRR Common-mode rejection ratio VCM = 2.7 V to 120 V, TA = –40 °C to +125 °C 140 160 dB
f = 50 kHz 85
Vos Offset voltage, input referred A1 devices 5 ±25 µV
A2 devices 3 ±20
A3 devices 3 ±15
A4, A5 devices 2 ±12
dVos/dT Offset voltage drift TA = –40 °C to +125 °C 0.2 µV/℃
PSRR Power supply rejection ratio, input referred VS = 2.7 V to 20 V, TA = –40 °C to +125 °C 0.05 ±0.5 µV/V
IB Input bias current IB+, VSENSE = 0 mV 10 20 30 µA
IB–, VSENSE = 0 mV 10 20 30
OUTPUT
G Gain A1 devices 20 V/V
A2 devices 50
A3 devices 100
A4 devices 200
A5 devices 500
Gain error A1, A2, A3 devices,
GND + 50 mV ≤ VOUT ≤ VS – 200 mV		 0.02 ±0.1 %
A4, A5 devices,
GND + 50 mV ≤ VOUT ≤ VS – 200 mV		 0.02 ±0.15
Gain error drift TA = –40 °C to +125 °C 1.5 5 ppm/°C
Nonlinearity error 0.01 %
Maximum capacitive load No sustained oscillations, no isolation resistor 500 pF
VOLTAGE OUTPUT
Swing to VS power supply rail RLOAD = 10 kΩ, TA = –40 °C to +125 °C VS – 0.07 VS – 0.2 V
Swing to ground RLOAD = 10 kΩ, VSENSE = 0 V, TA = –40 °C to +125 °C 0.005 0.025 V
FREQUENCY RESPONSE
BW Bandwidth A1 devices, CLOAD = 5 pF, VSENSE = 200 mV 1100 kHz
A2 devices, CLOAD = 5 pF, VSENSE = 80 mV 1100
A3 devices, CLOAD = 5 pF, VSENSE = 40 mV 900
A4 devices, CLOAD = 5 pF, VSENSE = 20 mV 850
A5 devices, CLOAD = 5 pF, VSENSE = 8 mV 800
SR Slew rate 2 V/µs
Settling time VOUT =4 V ± 0.1 V step, output settles to 0.5% 9 µs
VOUT =4 V ± 0.1 V step, output settles to 1% 5
NOISE
Ven Voltage noise density 50 nV/√Hz
POWER SUPPLY
VS Supply voltage TA = –40 °C to +125 °C 2.7 20 V
IQ Quiescent current, INA290 370 500 µA
TA = –40 °C to +125 °C 600
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