米6体育平台手机版

ZHCSR64C december 2022 – may 2023 INA351

PRODUCTION DATA

封装选项

机械数据 (封装 | 引脚)

DSG|8
- MPDS308C
RUG|10
- MPQF216A

散热焊盘机械数据 (封装 | 引脚)

DSG|8
- QFND141I

订购信息

7.6 Typical Characteristics

at T_A = 25°C, V_S = (V+) – (V–) = 5.5 V, V_IN = (V_IN+) – (V_IN–) = 0 V, R_L = 10 kΩ, C_L = 10 pF, V_REF = V_S / 2, V_CM = [(V_IN+) + (V_IN–)] / 2 = V_S / 2, V_OUT = V_S / 2 and G = 10 (unless otherwise noted)

G = 10, 20, 30, 50

N = 36

μ = 23 μV

σ = 0.180 mV

Figure 7-1 Typical Distribution of Input Referred Offset Voltage

T_A = 25°C

N = 72

μ = 0.33 pA

σ = 0.43 pA

Figure 7-3 Typical Distribution of Input Bias Current

T_A = 85°C

N = 72

μ = 3.3 pA

σ = 0.53 pA

Figure 7-5 Typical Distribution of Input Bias Current

G = 10

N = 36

μ = -0.30 μV/V

σ = 7.10 μV/V

Figure 7-7 Typical Distribution of CMRR

G = 30

N = 36

μ = –1.23 μV/V

σ = 7.52 μV/V

Figure 7-9 Typical Distribution of CMRR

G = 10

N = 36

μ = 0.002 %

σ = 0.02 %

Figure 7-11 Typical Distribution of Gain Error

G = 30

N = 36

μ = 0.0067 %

σ = 0.011 %

Figure 7-13 Typical Distribution of Gain Error

G = 10, 20, 30, 50

Figure 7-15 Input Referred Offset Voltage vs Temperature

Figure 7-17 Input Offset Current vs Temperature

Figure 7-19 Shutdown Quiescent Current vs Temperature

Figure 7-21 Gain Error vs Temperature

V+ = 2.75 V and V– = –2.75 V

Figure 7-23 Input Referred Offset Voltage vs Input Common-Mode Voltage

V+ = 2.75 V and V– = –2.75 V

Figure 7-25 Input Bias Current vs Input Common-Mode Voltage

V+ = 2.75 V and V– = –2.75 V

Figure 7-27 Quiescent Current vs Input Common-Mode Voltage

Figure 7-29 Quiescent Current vs Supply Voltage

Figure 7-31 Output Voltage vs Output Current (Sinking)

Figure 7-33 CMRR (Referred to Input) vs Frequency

Figure 7-35 PSRR– (Referred to Input) Vs Frequency

Figure 7-37 0.1 Hz to 10 Hz Voltage Noise in Time Domain

Figure 7-39 Maximum Output Voltage vs Frequency

V_S = 5.5 V	BW = 80 kHz	V_CM = 2.75 V
R_L = 100 kΩ	V_OUT = 1 V_RMS

Figure 7-41 THD + N Frequency

V_S = 5.5 V

G = 10

V_OUT = 100 mV_PP

Figure 7-43 Small-Signal Overshoot vs Capacitive Load

V_S = 5.5 V

G = 30

V_OUT = 100 mV_PP

Figure 7-45 Small-Signal Overshoot vs Capacitive Load

V+ = 2.75 V

V– = –2.75 V

G = 10

V_OUT = 2 V_PP

Figure 7-47 Large Signal Step Response

V+ = 2.75 V

V– = –2.75 V

G = 10

V_OUT = 2 V_PP

Figure 7-49 Large Signal Settling Time (Rising Edge)

V+ = 2.75 V

V– = –2.75 V

G = 10

V_OUT = 0.1 V_PP

Figure 7-51 Small-Signal Step Response

V+ = 2.75 V

V– = –2.75 V

G = 10

V_IN = 1 V_PP

Figure 7-53 Over-Load Recovery (Rising Edge)

V+ = 2.75 V

V– = –2.75 V

G = 10

V_IN = 0.6 V_PP

Figure 7-55 No Phase Reversal

V+ = +2.75 V

V– = –2.75 V

G = 10

Figure 7-57 Disable Response

V_S = 5.5 V

G = 10, 20, 30, 50

V_REF = V_S / 2

Figure 7-59 Input Common-Mode Voltage vs Output Voltage (High CMRR Region)

V_S = 5.5 V

G = 10, 20, 30, 50

V_REF = 0 V

Figure 7-61 Input Common-Mode Voltage vs Output Voltage (High CMRR Region)

V_S = 5.5 V

G = 10, 20, 30, 50

V_REF = V_S / 2

Figure 7-63 Input Common-Mode Voltage vs Output Voltage

V_S = 5.5 V

G = 10, 20, 30, 50

V_REF = 0 V

Figure 7-65 Input Common-Mode Voltage vs Output Voltage

G = 10, 20, 30, 50

N = 36

μ = 0.23 μV/°C

σ = 0.36 μV/°C

Figure 7-2 Typical Distribution of Input Referred Offset Drift

T_A = 25°C

N = 36

μ = –0.40 pA

σ = 0.47 pA

Figure 7-4 Typical Distribution of Input Offset Current

T_A = 85°C

N = 36

μ = 0.05 pA

σ = 0.30 pA

Figure 7-6 Typical Distribution of Input Offset Current

G = 20

N = 36

μ = -0.27 μV/V

σ = 7.20 μV/V

Figure 7-8 Typical Distribution of CMRR

G = 50

N = 36

μ = –1.16 μV/V

σ = 7.62 μV/V

Figure 7-10 Typical Distribution of CMRR

G = 20

N = 36

μ = -0.02 %

σ = 0.02 %

Figure 7-12 Typical Distribution of Gain Error

G = 50

N = 36

μ = 0.0035 %

σ = 0.012 %

Figure 7-14 Typical Distribution of Gain Error

Figure 7-16 Input Bias Current vs Temperature

Figure 7-18 Quiescent Current vs Temperature

Figure 7-20 Short Circuit Current vs Temperature

Figure 7-22 CMRR vs Temperature

V+ = 1.65 V and V– = –1.65 V

Figure 7-24 Input Referred Offset Voltage vs Input Common-Mode Voltage

V+ = 2.75 V and V– = –2.75 V

Figure 7-26 Input Offset Current vs Input Common-Mode Voltage

G = 10

Figure 7-28 Input Referred Offset Voltage vs Supply Voltage

Figure 7-30 Output Voltage vs Output Current (Sourcing)

Figure 7-32 Closed-Loop Gain vs Frequency

Figure 7-34 PSRR+ (Referred to Input) vs Frequency

Figure 7-36 Input Referred Voltage Noise Spectral Density

Figure 7-38 Closed-Loop Output Impedance vs Frequency

V_S = 5.5 V	BW = 80 kHz	V_CM = 2.75 V
R_L = 10 kΩ	V_OUT = 0.5 V_RMS

Figure 7-40 THD + N Frequency

Figure 7-42 Electromagnetic Interference Rejection Ratio Referred to Noninverting Input (EMIRR+) vs Frequency

V_S = 5.5 V

G = 20

V_OUT = 100 mV_PP

Figure 7-44 Small-Signal Overshoot vs Capacitive Load

V_S = 5.5 V

G = 50

V_OUT = 100 mV_PP

Figure 7-46 Small-Signal Overshoot vs Capacitive Load

V+ = 2.75 V

V– = –2.75 V

G = 10

V_OUT = 2 V_PP

Figure 7-48 Large Signal Settling Time (Falling Edge)

V+ = 2.75 V

V– = –2.75 V

G = 50

V_OUT = 2 V_PP

Figure 7-50 Large Signal Step Response

V+ = 2.75 V

V– = –2.75 V

G = 50

V_OUT = 0.1 V_PP

Figure 7-52 Small-Signal Step Response

V+ = 2.75 V

V– = –2.75 V

G = 10

V_IN = 1 V_PP

Figure 7-54 Over-Load Recovery (Falling Edge)

V+ = +2.75 V

V– = –2.75 V

G = 10

Figure 7-56 Enable Response

V_S = 3.3 V

G = 10, 20, 30, 50

V_REF = V_S / 2

Figure 7-58 Input Common-Mode Voltage vs Output Voltage (High CMRR Region)

V_S = 3.3 V

G = 10, 20, 30, 50

V_REF = 0 V

Figure 7-60 Input Common-Mode Voltage vs Output Voltage (High CMRR Region)

V_S = 3.3 V

G = 10, 20, 30, 50

V_REF = V_S / 2

Figure 7-62 Input Common-Mode Voltage vs Output Voltage

V_S = 3.3 V

G = 10, 20, 30, 50

V_REF = 0 V

Figure 7-64 Input Common-Mode Voltage vs Output Voltage