米6体育平台手机版

ZHCSJM1A April 2019 – June 2019 INA818

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7.7 Typical Characteristics

at T_A = 25°C, V_S = ±15 V, R_L = 10 kΩ, V_REF = 0 V, and G = 1 (unless otherwise noted)

N = 1555

Mean = 4.71 µV

Std. Dev. = 7.12 µV

Figure 1. Typical Distribution of Input Stage Offset Voltage

N = 1555	Mean = –3.18 µV	Std. Dev. = 41.26 µV

Figure 3. Typical Distribution of Output Stage Offset Voltage

45 units, 1 wafer lot

Figure 5. Input Stage Offset Voltage vs Temperature

N = 94	Mean = 37.13 pA	Std. Dev. = 57.65 pA
T_A = 25°C

Figure 7. Typical Distribution of Input Bias Current

N = 94	Mean = –38.82 pA	Std. Dev. = 47.24 pA

Figure 9. Typical Distribution of Input Offset Current

N = 94	G = 1

Figure 11. Input Offset Current vs Temperature

N = 94	Mean = 0.34 µV/V	Std. Dev. = 0.54 µV/V
G = 10

Figure 13. Typical CMRR Distribution

5 typical units	G = 10

Figure 15. CMRR vs Temperature

Figure 17. CMRR vs Frequency (RTI)

Figure 19. Positive PSRR vs Frequency (RTI)

Figure 21. Gain vs Frequency

Figure 23. Current Noise Spectral Density vs Frequency (RTI)

G = 1000

Figure 25. 0.1-Hz to 10-Hz RTI Voltage Noise

V_S = ±15 V

Figure 27. Input Bias Current vs Common-Mode Voltage

N = 94	Mean = 286 ppm	Std. Dev. = 204 ppm
G = 10

Figure 29. Typical Distribution of Gain Error G = 10

	G = 10

Figure 31. Gain Error vs Temperature

G = 1

Figure 33. Gain Nonlinearity

Figure 35. Offset Voltage vs Negative Common-Mode Voltage

Figure 37. Positive Output Voltage Swing vs Output Current

Figure 39. Short Circuit Current vs Temperature

500-kHz measurement bandwidth
1-V_RMS output voltage	100-kΩ load

Figure 41. THD+N vs Frequency

G = 1	R_L = 10 kΩ	C_L = 100 pF

Figure 43. Small-Signal Response

G = 100

R_L = 10 kΩ

C_L = 100 pF

Figure 45. Small-Signal Response

Figure 47. Large Signal Step Response

Figure 49. Differential-Mode EMI Rejection Ratio

V_S = 5 V

G = 1

Figure 51. Input Common-Mode Voltage vs Output Voltage

V_S = ±5 V

V_REF = 0 V

Figure 53. Input Common-Mode Voltage vs Output Voltage

N = 45

Mean = 0.0357 µV/°C

Std. Dev. = 0.099 µV/°C

Figure 2. Typical Distribution of Input Stage Offset Voltage Drift

N = 45	Mean = –1.49 µV/°C	Std. Dev. = 0.89 µV/°C

Figure 4. Typical Distribution of Output Stage Offset Voltage Drift

45 units, 1 wafer lots

Figure 6. Output Stage Offset Voltage vs Temperature

N = 94	Mean = –27.65 pA	Std. Dev. = 52.58 pA
T_A = 90°C

Figure 8. Typical Distribution of Input Bias Current

N = 94	G = 1

Figure 10. Input Bias Current vs Temperature

N = 94	Mean = 3.23 µV/V	Std. Dev. = 5.38 µV/V
G = 1

Figure 12. Typical CMRR Distribution

5 typical units	G = 1

Figure 14. CMRR vs Temperature

V_S = 36 V

Figure 16. Input Current vs Input Overvoltage

	1-kΩ source imbalance

Figure 18. CMRR vs Frequency (RTI)

Figure 20. Negative PSRR vs Frequency (RTI)

Figure 22. Voltage Noise Spectral Density vs Frequency (RTI)

G = 1

Figure 24. 0.1-Hz to 10-Hz RTI Voltage Noise

Figure 26. 0.1-Hz to 10-Hz RTI Current Noise

N = 94	Mean = –48 ppm	Std. Dev. = 58 ppm
G = 1

Figure 28. Typical Distribution of Gain Error G = 1

	G = 1

Figure 30. Gain Error vs Temperature

Figure 32. Supply Current vs Temperature

G = 10

Figure 34. Gain Nonlinearity

Figure 36. Offset Voltage vs Positive Common-Mode Voltage

Figure 38. Negative Output Voltage Swing vs Output Current

Figure 40. Large-Signal Frequency Response

Figure 42. Overshoot vs Capacitive Loads

G = 10	R_L = 10 kΩ	C_L = 100 pF

Figure 44. Small-Signal Response

G = 1000

R_L = 10 kΩ

C_L = 100 pF

Figure 46. Small-Signal Response

Figure 48. Closed-Loop Output Impedance

Figure 50. Common-Mode EMI Rejection Ratio

V_S = 5 V

G = 100

Figure 52. Input Common-Mode Voltage vs Output Voltage

V_S = ±15 V

V_REF = 0 V

Figure 54. Input Common-Mode Voltage vs Output Voltage