米6体育平台手机版

ZHCSNH8B July 2021 – November 2021 INA823

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D|8
- MSOI002K
DGK|8
- MPDS028E

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7.6 Typical Characteristics

at T_A = 25°C, V_S = ±15 V, R_L = 10 kΩ, C_L = 0 pF, V_CM = V_REF = 0 V, and G = 1 (unless otherwise noted)

Table 7-1 Table of Graphs

FIGURE TITLE	FIGURE NUMBER
Typical Distribution Graphs
Typical Distribution of Input Stage Offset Voltage	Figure 7-1
Typical Distribution of Input Stage Offset Voltage Drift	Figure 7-2
Typical Distribution of Output Stage Offset Voltage	Figure 7-3
Typical Distribution of Output Stage Offset Voltage Drift	Figure 7-4
Typical Distribution of Inverting Input Bias Current	Figure 7-5
Typical Distribution of Noninverting Input Bias Current	Figure 7-6
Typical Distribution of Input Offset Current	Figure 7-7
Typical CMRR Distribution, G = 1	Figure 7-8
Typical CMRR Distribution, G = 10	Figure 7-9
Typical Gain Error Distribution	Figure 7-10
vs Temperature Graphs
Input Stage Offset Voltage vs Temperature	Figure 7-11
Output Stage Offset Voltage vs Temperature	Figure 7-12
Input Bias Current vs Temperature	Figure 7-13
Input Offset Current vs Temperature	Figure 7-14
CMRR vs Temperature, G = 1	Figure 7-15
CMRR vs Temperature, G = 10	Figure 7-16
Gain Error vs Temperature, G = 1	Figure 7-17
Gain Error vs Temperature, G = 100	Figure 7-18
Supply Current vs Temperature	Figure 7-19
AC Performance Graphs
Closed-Loop Gain vs Frequency	Figure 7-20
CMRR vs Frequency (RTI)	Figure 7-21
CMRR vs Frequency (RTI, 1-kΩ source imbalance)	Figure 7-22
Positive PSRR vs Frequency (RTI)	Figure 7-23
Negative PSRR vs Frequency (RTI)	Figure 7-24
Voltage Noise Spectral Density vs Frequency (RTI)	Figure 7-25
Current Noise Spectral Density vs Frequency (RTI)	Figure 7-26
0.1-Hz to 10-Hz RTI Voltage Noise	Figure 7-27
0.1-Hz to 10-Hz RTI Voltage Noise, G = 1000	Figure 7-28
Small-Signal Response, G = 1	Figure 7-29
Small-Signal Response, G = 10	Figure 7-30
Small-Signal Response, G = 100	Figure 7-31
Small-Signal Response, G = 1000	Figure 7-32
Overshoot vs Capacitive Loads	Figure 7-33
Large-Signal Step Response	Figure 7-34
Settling Time vs Step Size	Figure 7-35
Large-Signal Frequency Response	Figure 7-36
Closed-Loop Output Impedance vs Frequency	Figure 7-37
Input and Output Voltage Graphs
Input Current vs Input Overvoltage	Figure 7-38
Gain Nonlinearity, G = 1	Figure 7-39
Gain Nonlinearity, G = 10	Figure 7-40
Gain Nonlinearity, G = 100	Figure 7-41
Gain Nonlinearity, G = 1000	Figure 7-42
Positive Input Bias Current vs Common‑Mode Voltage (V_S–)	Figure 7-43
Positive Input Bias Current vs Common‑Mode Voltage (V_S+)	Figure 7-44
Negative Input Bias Current vs Common‑Mode Voltage (V_S–)	Figure 7-45
Negative Input Bias Current vs Common‑Mode Voltage (V_S+)	Figure 7-46
Offset Voltage vs Common-Mode Voltage, V_S = 30 V	Figure 7-47
Offset Voltage vs Common-Mode Voltage, V_S = 2.7 V	Figure 7-48
Positive Output Voltage Swing vs Output Current, V_S = 30 V	Figure 7-49
Negative Output Voltage Swing vs Output Current, V_S = 30 V	Figure 7-50
Positive Output Voltage Swing vs Output Current, V_S = 2.7 V	Figure 7-51
Negative Output Voltage Swing vs Output Current, V_S = 2.7 V	Figure 7-52
Input Common-Mode Voltage vs Output Voltage, V_S = 2.7 V, G = 1	Figure 7-53
Input Common-Mode Voltage vs Output Voltage, V_S = 2.7 V, G = 1	Figure 7-54
Input Common-Mode Voltage vs Output Voltage, V_S = 5 V, G = 1	Figure 7-55
Input Common-Mode Voltage vs Output Voltage, V_S = 5 V, G = 100	Figure 7-56
Input Common-Mode Voltage vs Output Voltage, V_S = 24 V and V_S = 30 V, G = 1	Figure 7-57
Input Common-Mode Voltage vs Output Voltage, V_S = 24 V and V_S = 30 V, G = 10	Figure 7-58

N = 1225

Mean = 3.63 μV

Std Dev = 18.0 μV

Figure 7-1 Typical Distribution of Input Stage Offset Voltage

N = 1225

Mean = 48.0 μV

Std Dev = 92.4 μV

Figure 7-3 Typical Distribution of Output Stage Offset Voltage

N = 1200

Mean = 1.21 nA

Std Dev = 0.384 nA

Figure 7-5 Typical Distribution of Inverting Input Bias Current

N = 1170

Mean = –0.092 nA

Std Dev = 0.35 nA

Figure 7-7 Typical Distribution of Input Offset Current

N = 1225	Mean = –0.0599 μV/V	Std. Dev = 0.710 μV/V
	G = 10

Figure 7-9 Typical CMRR Distribution

Figure 7-11 Input Stage Offset Voltage vs Temperature

Figure 7-13 Input Bias Current vs Temperature

G = 1

Figure 7-15 CMRR vs Temperature

G = 1

Average of 120 units

Normalized at +25°C

Figure 7-17 Gain Error vs Temperature

Figure 7-19 Supply Current vs Temperature

Figure 7-21 CMRR vs Frequency (RTI)

Figure 7-23 Positive PSRR vs Frequency (RTI)

Figure 7-25 Voltage Noise Spectral Density vs Frequency (RTI)

Figure 7-27 0.1-Hz to 10-Hz RTI Voltage Noise

G = 1

R_L = 10 kΩ

C_L = 100 pF

Figure 7-29 Small-Signal Response

G = 100

R_L = 10 kΩ

C_L = 100 pF

Figure 7-31 Small-Signal Response

Figure 7-33 Overshoot vs Capacitive Loads

Figure 7-35 Settling Time vs Step Size

Figure 7-37 Closed-Loop Output Impedance vs Frequency

Figure 7-39 Gain Nonlinearity

Figure 7-41 Gain Nonlinearity

Figure 7-43 Positive Input Bias Current vs Common‑Mode Voltage (V_S–)

Figure 7-45 Negative Input Bias Current vs Common‑Mode Voltage (V_S–)

V_S = ±15 V

Figure 7-47 Offset Voltage vs Common-Mode Voltage

V_S = ±15 V

Figure 7-49 Positive Output Voltage Swing vs Output Current

V_S = ±1.35 V

Figure 7-51 Positive Output Voltage Swing vs Output Current

V_S = 2.7 V

G = 1

Figure 7-53 Input Common-Mode Voltage vs Output Voltage

V_S = 5 V

G = 1

Figure 7-55 Input Common-Mode Voltage vs Output Voltage

G = 1

Figure 7-57 Input Common-Mode Voltage vs Output Voltage

N = 30

Mean = –0.024 μV/ºC

Std Dev = 0.177 μV//ºC

Figure 7-2 Typical Distribution of Input Stage Offset Voltage Drift

N = 30

Mean = 0.17 μV/ºC

Std Dev = 0.795 μV/ºC

Figure 7-4 Typical Distribution of Output Stage Offset Voltage Drift

N = 1200

Mean = 1.11 nA

Std Dev = 0.368 nA

Figure 7-6 Typical Distribution of Noninverting Input Bias Current

N = 1225

Mean = –0.22 μV/V

Std Dev = 6.95 μV/V

Figure 7-8 Typical CMRR Distribution

N = 550	Mean = –0.0334 %	Std. Dev = 0.0433 %
	G = 10

Figure 7-10 Typical Gain Error Distribution

Figure 7-12 Output Stage Offset Voltage vs Temperature

Figure 7-14 Input Offset Current vs Temperature

G = 10

Figure 7-16 CMRR vs Temperature

G = 100

Average of 120 units

Normalized at +25°C

Figure 7-18 Gain Error vs Temperature

Figure 7-20 Closed-Loop Gain vs Frequency

Figure 7-22 CMRR vs Frequency (RTI, 1-kΩ source imbalance)

Figure 7-24 Negative PSRR vs Frequency (RTI)

Figure 7-26 Current Noise Spectral Density vs Frequency (RTI)

Figure 7-28 0.1-Hz to 10-Hz RTI Voltage Noise

G = 10

R_L = 10 kΩ

C_L = 100 pF

Figure 7-30 Small-Signal Response

G = 1000

R_L = 10 kΩ

C_L = 100 pF

Figure 7-32 Small-Signal Response

Figure 7-34 Large-Signal Step Response

Figure 7-36 Large-Signal Frequency Response

V_S = ±15 V

Figure 7-38 Input Current vs Input Overvoltage

Figure 7-40 Gain Nonlinearity

Figure 7-42 Gain Nonlinearity

Figure 7-44 Positive Input Bias Current vs Common‑Mode Voltage (V_S+)

Figure 7-46 Negative Input Bias Current vs Common‑Mode Voltage (V_S+)

V_S = ±1.35 V

Figure 7-48 Offset Voltage vs Common-Mode Voltage

V_S = ±15 V

Figure 7-50 Negative Output Voltage Swing vs Output Current

V_S = ±1.35 V

Figure 7-52 Negative Output Voltage Swing vs Output Current

V_S = 2.7 V

G = 100

Figure 7-54 Input Common-Mode Voltage vs Output Voltage

V_S = 5 V

G = 100

Figure 7-56 Input Common-Mode Voltage vs Output Voltage

G > 10

Figure 7-58 Input Common-Mode Voltage vs Output Voltage