8.3.1 Inside the INA826

See the Functional Block Diagram section for a simplified representation of the INA826. A more detailed diagram, shown in Figure 58, provides additional insight into the INA826 operation.

Each input is protected by two field-effect transistors (FETs) that provide a low series resistance under normal signal conditions, and preserve excellent noise performance. When excessive voltage is applied, these transistors limit input current to approximately 8 mA.

The differential input voltage is buffered by Q₁ and Q₂ and is impressed across R_G, causing a signal current to flow through R_G, R₁, and R₂. The output difference amplifier, A₃, removes the common-mode component of the input signal and refers the output signal to the REF terminal.

The equations shown in Figure 58 describe the output voltages of A₁ and A₂. The V_BE and voltage drop across R₁ and R₂ produce output voltages on A₁ and A₂ that are approximately 0.8 V higher than the input voltages.

Figure 58. INA826 Simplified Circuit Diagram