ZHCSGB6A May   2017  – June 2017 INA826S

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Inside the INA826S
      2. 7.3.2 Setting the Gain
        1. 7.3.2.1 Gain Drift
      3. 7.3.3 Offset Trimming
      4. 7.3.4 Input Common-Mode Range
      5. 7.3.5 Input Protection
      6. 7.3.6 Input Bias Current Return Path
      7. 7.3.7 Reference Pin (REF)
      8. 7.3.8 Shutdown (EN and ENREF) Pins
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
    1. 9.1 Low-Voltage Operation
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11器件和文档支持
    1. 11.1 文档支持
      1. 11.1.1 相关文档
    2. 11.2 接收文档更新通知
    3. 11.3 社区资源
    4. 11.4 商标
    5. 11.5 静电放电警告
    6. 11.6 Glossary
  12. 12机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Supply voltage –20 20 V
Voltage Signal input pins (–VS) – 40 (+VS) + 40 V
REF pin –20 +20
ENREF pin (–VS) – 0.3 (+VS) + 0.3
EN pin (–VS) – 0.3 VENREF + 0.3
Current Signal input pins –10 10 mA
REF pin –10 10
ENREF pin –1 1
EN pin –1 1
Output short-circuit(2) Continuous
Temperature Operating, TA –50 150 °C
Junction, TJ 175
Storage, Tstg –65 150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Short-circuit to VS / 2.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2500 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
Supply voltage Single-supply 3 36 V
Dual-supply ±1.5 ±18
Specified temperature –40 125 °C

6.4 Thermal Information

THERMAL METRIC(1) INA826S UNIT
VSON (DRC)
10 PINS
RθJA Junction-to-ambient thermal resistance 51.9 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 58.2 °C/W
RθJB Junction-to-board thermal resistance 25.8 °C/W
ψJT Junction-to-top characterization parameter 2.0 °C/W
ψJB Junction-to-board characterization parameter 25.8 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 8.6 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.5 Electrical Characteristics

at TA = 25°C, VS = ±15 V, RL = 10 kΩ, VREF = 0 V, and G = 1 (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INPUT
VOSI Input stage offset voltage(1) RTI 40 150 µV
vs temperature, TA = –40°C to +125°C 0.4 2 µV/°C
VOSO Output stage offset voltage(1) RTI 200 1000 µV
vs temperature, TA = –40°C to +125°C 2 5 µV/°C
PSRR Power-supply rejection ratio G = 1, RTI 90 124 dB
G = 10, RTI 100 130
G = 100, RTI 110 140
G = 1000, RTI 120 140
zid Differential impedance 20 || 1 GΩ || pF
zic Common-mode impedance 10 || 5 GΩ || pF
RFI filter, –3-dB frequency 20 MHz
VCM Operating input range(2) V– (V+) – 1 V
VS = ±3 V to ±18 V, TA = –40°C to +125°C See Figure 12 to Figure 19
Input overvoltage range TA = –40°C to 125°C ±40 V
CMRR Common-mode rejection ratio At dc to 60 Hz, RTI G = 1, VCM = (V–) to (V+) – 1 V 82 95 dB
G = 10, VCM = (V–) to (V+) – 1 V 104 115
G = 100, VCM = (V–) to (V+) – 1 V 120 130
G = 1000, VCM = (V–) to (V+) – 1 V 120 130
G = 1, VCM = (V–) to (V+) – 1 V,
TA = –40°C to +125°C		 80
At 5 kHz, RTI G = 1, VCM = (V–) to (V+) – 1 V 84
G = 10, VCM = (V–) to (V+) – 1 V 100
G = 100, VCM = (V–) to (V+) – 1 V 105
G = 1000, VCM = (V–) to (V+) – 1 V 105
BIAS CURRENT
IB Input bias current VCM = VS / 2 35 65 nA
TA = –40°C to +125°C 95
IOS Input offset current VCM = VS / 2 0.7 5 nA
TA = –40°C to +125°C 10
NOISE VOLTAGE
eNI Input stage voltage noise(4) f = 1 kHz, G = 100, RS = 0 Ω 18 nV/√Hz
fB = 0.1 Hz to 10 Hz, G = 100, RS = 0 Ω 0.52 µVPP
eNO Output stage voltage noise(4) f = 1 kHz, G = 1, RS = 0 Ω 110 nV/√Hz
fB = 0.1 Hz to 10 Hz, G = 1, RS = 0 Ω 3.3 µVPP
In Noise current f = 1 kHz 100 fA/√Hz
fB = 0.1 Hz to 10 Hz 5 pAPP
GAIN
G Gain equation 1 + (49.4 kΩ / RG) V/V
G Range of gain 1 1000 V/V
GE Gain error G = 1, VO = ±10 V ±0.003% ±0.020%
G = 10, VO = ±10 V ±0.03% ±0.15%
G = 100, VO = ±10 V ±0.04% ±0.15%
G = 1000, VO = ±10 V ±0.04% ±0.15%
Gain vs temperature(3) G = 1, TA = –40°C to +125°C ±0.1 ±1 ppm/°C
G > 1, TA = –40°C to +125°C ±10 ±35
Gain nonlinearity G = 1 to 100, VO = –10 V to 10 V 1 5 ppm
G = 1000, VO = –10 V to 10 V 5 20
OUTPUT
Voltage swing RL = 10 kΩ (V–) + 0.1 (V+) – 0.15 V
Load capacitance stability 1000 pF
ZO Open-loop output impedance See Figure 59
ISC Short-circuit current Continuous to VS / 2 ±16 mA
FREQUENCY RESPONSE
BW Bandwidth, –3 dB G = 1 1 MHz
G = 10 500 kHz
G = 100 60
G = 1000 6
SR Slew rate G = 1, VSTEP = 10 V 1 V/µs
G = 100, VSTEP = 10 V 1
tS Settling time 0.01% G = 1, VSTEP = 10 V 12 µs
G = 10, VSTEP = 10 V 12
G = 100, VSTEP = 10 V 24
G = 1000, VSTEP = 10 V 224
0.001% G = 1, VSTEP = 10 V 14
G = 10, VSTEP = 10 V 14
G = 100, VSTEP = 10 V 31
G = 1000, VSTEP = 10 V 278
REFERENCE INPUT
RIN Input impedance 100 kΩ
Voltage range (V–) (V+) V
Gain to output 1 V/V
Reference gain error 0.01%
ENABLE INPUT
Enable threshold voltage Referenced to ENREF pin –0.75 V
TA = –40°C to +125°C –1.0
Disable threshold voltage Referenced to ENREF pin –0.7 V
TA = –40°C to +125°C –0.40
EN pin input current VENREF = 1.5 V, VEN = 0 V 3 µA
ENREF pin input current VENREF = 1.5 V, VEN = 0 V –3 µA
EN pin voltage range V– VENREF V
ENREF voltage range (V–) + 1.5 V V+ V
Enable delay 100 µs
POWER SUPPLY
VS Power-supply voltage Single 3 36 V
Dual ±1.5 ±18
IQ Quiescent current VIN = 0 V 200 250 µA
TA = –40°C to +125°C 320
IQSD Shutdown current VS = 3 V to 36 V, VIN = 0 V 2 5 µA
TA = –40°C to +125°C 6
TEMPERATURE RANGE
Specified –40 125 °C
Operating –50 150 °C
(1) Total offset, referred-to-input (RTI): VOS = (VOSI) + (VOSO / G).
(2) Input voltage range of the INA826S input stage. The input range depends on the common-mode voltage, differential voltage, gain, and reference voltage.
(3) The values specified for G > 1 do not include the effects of the external gain-setting resistor, RG.
(4) Total RTI voltage noise is equal to: INA826S q_total_rti_noise_bos562.gif .

6.6 Typical Characteristics

at TA = 25°C, VS = ±15 V, RL = 10 kΩ, VREF = 0 V, and G = 1 (unless otherwise noted)
INA826S C001_SBOS770.png
1024 units
Figure 1. Typical Distribution of
Input Offset Voltage
INA826S C003_SBOS770.png
1024 units
Figure 3. Typical Distribution of
Output Offset Voltage
INA826S C005_SBOS770.png
1024 units
Figure 5. Typical Distribution of
Input Bias Current
INA826S C007_SBOS770.png
1024 units
Figure 7. Typical Distribution of CMRR (G = 1)
INA826S C009_SBOS770.png
1024 units
Figure 9. Typical Distribution of Gain Error (G = 1)
INA826S C011_SBOS770.png
5977 units
Figure 11. Typical Gain Error Drift Distribution
(G = 1)
INA826S D036_SBOS770.gif
Single supply, VS = 3 V, G = 100
Figure 13. Input Common-Mode Voltage vs Output Voltage
INA826S D037_SBOS770.gif
Single supply, VS = 5 V, G = 100
Figure 15. Input Common-Mode Voltage vs Output Voltage
INA826S D038_SBOS770.gif
Dual supply, VS = ±5 V, VREF = 0 V
Figure 17. Input Common-Mode Voltage vs Output Voltage
INA826S D040_SBOS770.gif
Dual supply, VS = ±15 V and ±12 V, G = 100, VREF = 0 V
Figure 19. Input Common-Mode Voltage vs Output Voltage
INA826S D064_SBOS770.gif
G = 1, VS = ±15 V, RS = 10 kΩ
Figure 21. Input Current vs Input Voltage
with 10-kΩ Resistance
INA826S D002_SBOS770.gif
Figure 23. CMRR vs Frequency
(RTI, 1-kΩ Source Imbalance)
INA826S D004_SBOS770.gif
Figure 25. Negative PSRR vs Frequency (RTI)
INA826S D019_SBOS770.gif
Figure 27. Voltage Noise Spectral Density
vs Frequency (RTI)
INA826S D007_SBOS770.gif
Figure 29. 0.1-Hz to 10-Hz RTI Voltage Noise (G = 1)
INA826S D008_SBOS770.gif
Figure 31. 0.1-Hz to 10-Hz RTI Current Noise
INA826S D055_SBOS770.gif
VS = ±15 V
Figure 33. Input Bias Current vs Common-Mode Voltage
INA826S D053_SBOS770.gif
Figure 35. Input Offset Current vs Temperature
INA826S D054_SBOS770.gif
Figure 37. Gain Error vs Temperature
(G > 1)
INA826S D043_SBOS770.gif
Figure 39. Supply Current vs Temperature
INA826S D022_SBOS770.gif
Figure 41. Gain Nonlinearity (G = 10)
INA826S D024_SBOS770.gif
Figure 43. Gain Nonlinearity (G = 1000)
INA826S D058_SBOS770.gif
VS = ±15 V
Figure 45. Offset Voltage vs
Positive Common-Mode Voltage
INA826S D060_SBOS770.gif
VS = 3 V
Figure 47. Offset Voltage vs
Positive Common-Mode Voltage
INA826S D046_SBOS770.gif
VS = ±15 V
Figure 49. Negative Output Voltage Swing
vs Output Current
INA826S D049_SBOS770.gif
VS = 3 V
Figure 51. Negative Output Voltage Swing
vs Output Current
INA826S D061_SBOS770.gif
Figure 53. Settling Time vs Step Size
(VS = ±15 V)
INA826S D009_SBOS770.gif
G = 1, RL = 1 kΩ, CL = 100 pF
Figure 55. Small-Signal Response
INA826S D011_SBOS770.gif
G = 100, RL = 10 kΩ, CL = 100 pF
Figure 57. Small-Signal Response
INA826S D062_SBOS770.gif
Figure 59. Open-Loop Output Impedance vs Frequency
INA826S C101_SBOS770.png
ENREF pin tied to 5 V
Figure 61. Enable Output Response
INA826S C002_SBOS770.png
5977 units
Figure 2. Typical Distribution of
Input Offset Voltage Drift
INA826S C004_SBOS770.png
5977 units
Figure 4. Typical Distribution of
Output Offset Voltage Drift
INA826S C006_SBOS770.png
1024 units
Figure 6. Typical Distribution of
Input Offset Current
INA826S C008_SBOS770.png
1024 units
Figure 8. Typical Distribution of CMRR (G = 100)
INA826S C010_SBOS770.png
1024 units
Figure 10. Gain Error (G = 10)
INA826S D035_SBOS770.gif
Single supply, VS = 3 V, G = 1
Figure 12. Input Common-Mode Voltage vs Output Voltage
INA826S D034_SBOS770.gif
Single supply, VS = 5 V, G = 1
Figure 14. Input Common-Mode Voltage vs Output Voltage
INA826S D039_SBOS770.gif
Dual supply, VS = ±3.3 V, VREF = 0 V
Figure 16. Input Common-Mode Voltage vs Output Voltage
INA826S D040_SBOS770.gif
Dual supply, VS = ±15 V and ±12 V, G = 1, VREF = 0 V
Figure 18. Input Common-Mode Voltage vs Output Voltage
INA826S D065_SBOS770.gif
G = 1, VS = ±15 V, RS = 0 Ω
Figure 20. Input Current vs Input Voltage
INA826S D001_SBOS770.gif
Figure 22. CMRR vs Frequency (RTI)
INA826S D003_SBOS770.gif
Figure 24. Positive PSRR vs Frequency (RTI)
INA826S D005_SBOS770.gif
Figure 26. Gain vs Frequency
INA826S D020_SBOS770.gif
Figure 28. Current Noise Spectral Density vs Frequency (RTI)
INA826S D006_SBOS770.gif
Figure 30. 0.1-Hz to 10-Hz RTI Voltage Noise (G = 1000)
INA826S D056_SBOS770.gif
VS = 3 V
Figure 32. Input Bias Current vs Common-Mode Voltage
INA826S D033_SBOS770.gif
Figure 34. Input Bias Current vs Temperature
INA826S D031_SBOS770.gif
Figure 36. Gain Error vs Temperature
(G = 1)
INA826S D032_SBOS770.gif
Figure 38. CMRR vs Temperature (G = 1)
INA826S D021_SBOS770.gif
Figure 40. Gain Nonlinearity (G = 1)
INA826S D023_SBOS770.gif
Figure 42. Gain Nonlinearity (G = 100)
INA826S D057_SBOS770.gif
VS = ±15 V
Figure 44. Offset Voltage vs
Negative Common-Mode Voltage
INA826S D059_SBOS770.gif
VS = 3 V
Figure 46. Offset Voltage vs
Negative Common-Mode Voltage
INA826S D045_SBOS770.gif
VS = ±15 V
Figure 48. Positive Output Voltage Swing
vs Output Current
INA826S D048_SBOS770.gif
VS = 3 V
Figure 50. Positive Output Voltage Swing
vs Output Current
INA826S D014_SBOS770.gif
Figure 52. Large-Signal Frequency Response
INA826S D013_SBOS770.gif
Figure 54. Small-Signal Response vs
Capacitive Loads (G = 1)
INA826S D010_SBOS770.gif
G = 10, RL = 10 kΩ, CL = 100 pF
Figure 56. Small-Signal Response
INA826S D012_SBOS770.gif
G = 1000, RL = 10 kΩ, CL = 100 pF
Figure 58. Small-Signal Response
INA826S D063_SBOS770.gif
Figure 60. Change in Input Offset Voltage vs Warm-Up Time
INA826S C102_SBOS770.png
ENREF pin tied to 5 V
Figure 62. Disable Output Response
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