ZHCSOW3 September   2020 INA848

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Topology
      2. 8.3.2 Input Common-Mode Range
      3. 8.3.3 Input Protection
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Filter Pin
        1. 9.1.1.1 RC Filter Network
        2. 9.1.1.2 RLC Filter Network
      2. 9.1.2 Input Bias Current Return Path
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Reference Pin
        2. 9.2.2.2 Noise Analysis
          1. 9.2.2.2.1 Reference Voltage Noise Contribution
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 支持资源
    4. 12.4 Trademarks
    5. 12.5 静电放电警告
    6. 12.6 术语表
  13. 13Mechanical, Packaging, and Orderable Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

9.2.1 Design Requirements

For this application, the design requirements are:

  • Differential input signal of VDIFF = 2.5 mV
  • Common-mode input voltage of VCM = 10 V
  • Power-supply voltage of VS = ± 15 V
  • Reference voltage buffered to VREF = 2.5 V
  • Output range within 0 V to 5 V
  • First-order filter stage with ‒3-dB frequency of 27 kHz
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