Table 9-2 show the typical signal-to-noise (SNR) and total harmonic distortion (THD) of the INA851 driving the ADS8900B SAR ADC at full-scale range and at different gain configurations. The RC filter combination (R_FIL, C_FIL) shown in Figure 9-6 helps attenuate the nonlinear charge kickback of the ADC and optimize for best THD performance. The combination of the RC filter and the feedback capacitor C_FB allow for the best trade-off between harmonic distortion and maintaining stability of the FDA. Low voltage-coefficient C0G capacitors are used everywhere in the signal path (C_FB, C_FIL) for the low-distortion properties.

For other bandwidth requirements, adjust the feedback capacitor accordingly, and verify the circuit performance using a SPICE simulation using the INA851 TINA-TI™ SPICE Model. The amplifier output voltage must settle within the ADC bit accuracy during the ADC acquisition time window. Verify the desired circuit is stable; that is, the FDA has more than a 45º phase margin.

G = 0.2 V/V, fIN = 1 kHz, SNR = 100.73 dB, THD = –117.28 dB

Figure 9-7 Noise Performance FFT Plots for G = 0.2 V/V

G = 1 V/V, fIN = 1 kHz, SNR = 100.6 dB, THD = –122.74 dB

Figure 9-8 Noise Performance FFT Plots for G = 1 V/V