ZHCSQ83A March   2022  – October 2022 INA851

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Related Products
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Adjustable Gain Setting
        1. 8.3.1.1 Gain Drift
      2. 8.3.2 Offset Voltage
      3. 8.3.3 Input Common-Mode Range
      4. 8.3.4 Input Protection
      5. 8.3.5 Output Clamping
      6. 8.3.6 Low Noise
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Output Common-Mode Pin
      2. 9.1.2 Output-Stage Gain Selection and Noise-Gain Shaping
      3. 9.1.3 Input Bias Current Return Path
      4. 9.1.4 Thermal Effects due to Power Dissipation
    2. 9.2 Typical Applications
      1. 9.2.1 Three-Pin Programmable Logic Controller (PLC)
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 应用曲线
      2. 9.2.2 20-Bit, 1-MSPS ADS8900B Driver Circuit With FDA Noise Filter
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Application Curves
      3. 9.2.3 24-Bit, 200 kSPS, Delta-Sigma ADS127L11 ADC Driver Circuit With FDA Noise Filter
        1. 9.2.3.1 Design Requirements
        2. 9.2.3.2 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Development Support
        1. 10.1.1.1 PSpice® for TI
        2. 10.1.1.2 TINA-TI™ Simulation Software (Free Download)
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 接收文档更新通知
    4. 10.4 支持资源
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 术语表
  11. 11Mechanical, Packaging, and Orderable Information

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8.3.6 Low Noise

An output noise calculation helps design a low-noise circuit to drive high-precision ADC applications and optimize the signal-to-noise ratio (SNR).

Figure 8-14 shows a simplified noise model for the INA851. The eNO noise refers to the input resistor network of the FDA. This term incorporates the thermal noise of the internal feedback resistors, and the interaction of the internal current noise density of the output stage with the internal feedback resistors.

Figure 8-14 Simplified Noise Model for the INA851

The internal feedback resistor network is considered in the eNO specification; therefore, the calculation of the total input-referred noise, eN(RTI), is simplified to the following equation:

Equation 4. e N ( R T I ) = e N I 2 + e N O ( G O U T = 1   o r   G O U T = 0.2 ) G I N 2

The total output-referred noise, eN(RTO), multiplies directly by the output stage gain, GOUT, by GOUT = 0.2 V/V or GOUT = 1 V/V respectively, as shown in the following equation:

Equation 5. e N ( R T O ) = ( e N I × G I N × 0.2   V / V   o r   1   V / V ) 2 + ( e N O G O U T = 1   o r   G O U T = 0.2 × 0.2   V / V   o r   1   V / V ) 2
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