ZHCSQ83A March 2022 – October 2022 INA851
PRODUCTION DATA
Figure 8-2 shows that the INA851 input-stage gain is set by a single external resistor (RG) connected between the RG pins. The gain of the output stage can be set to a unity gain of 1 V/V by floating the G02+ and G02– pins, or to an attenuating gain of 0.2 V/V by shorting those pins to the respective OUT+ and OUT– pins.
If the output stage is in the unity gain configuration, the value of RG is selected according to the following equation:
When OUT+ is shorted to G02+ (pin 11 to pin 12) and OUT– is shorted to G02– (pin 9 to pin 10) so that the output stage is in the attenuating configuration, the gain equation becomes:
Table 8-1 lists several commonly used gains and resistor values, as well as the additional gain error that is contributed by the gain resistors. The 6-kΩ term in the gain equation is a result of the sum of the two internal 3-kΩ feedback resistors. These on-chip resistors are laser-trimmed to accurate absolute values. The accuracy and temperature coefficients of these resistors are included in the gain accuracy and drift specifications of the INA851. The 5-kΩ and 1.25-kΩ resistors used in the output stage are ratiometrically matched to achieve stable 1-V/V and 0.2-V/V gain terms; although, the resistor values can shift up to 15%, depending on production.
| DESIRED GAIN (V/V) |
RG
(Ω) |
NEAREST 1% RG
(Ω) |
CALCULATED GAIN (V/V) | CONTRIBUTED GAIN ERROR (%) |
|---|---|---|---|---|
| 0.2 | NC, short OUT+ to G02+ and OUT– to G02– |
NC | 0.200 | N/A |
| 0.5 | 4 k, short OUT+ to G02+ and OUT– to G02– |
4.02 k | 0.499 | 0.30 |
| 1 | NC | NC | 1.000 | N/A |
| 2 | 6 k | 5.97 k | 2.005 | –0.25 |
| 5 | 1.5 k | 1.5 k | 5.000 | 0.00 |
| 10 | 666.67 | 665 | 10.023 | –0.23 |
| 20 | 315.79 | 316 | 19.987 | 0.06 |
| 50 | 122.45 | 124 | 49.387 | 1.23 |
| 100 | 60.61 | 60.4 | 100.338 | –0.34 |
| 200 | 30.15 | 30.1 | 200.336 | –0.17 |
| 500 | 12.02 | 12.1 | 496.868 | 0.63 |
| 1000 | 6.01 | 6.04 | 994.377 | 0.56 |
| 10000 | 600 m | 604 m | 9934.775 | 0.65 |
As shown in Figure 8-2 and explained in more detail in Section 9.4, make sure to connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, and to place these capacitors as close as possible to the device pins.