ZHCSQ83A March 2022 – October 2022 INA851
PRODUCTION DATA
The application circuit in Figure 9-6 shows the schematic of a complete input and reference driver circuit for the ADS8900B, a 20-bit, precision, 1-MSPS, successive approximation register (SAR), analog-to-digital converter (ADC). This circuit is used to measure the driving capability of the INA851 with the ADS8900B ADC.
To test the complete dynamic range of the circuit, the common-mode voltage VOCM of the input of the ADC is established at a value of VREF / 2.
To exclude noise caused by supply voltage, the test circuit uses the TPS7A4700, a low-noise 4-µVRMS, RF LDO voltage regulator, to generate the 5.2-V supply rail.
For VOCM, the circuit uses the REF5050, a low-noise, low-drift, 5-V reference, a 20k-20k voltage divider to establish VREF/2 and an additional RC filter (10 Ω, 150 pF) into the VOCM pin. See also the ADS8900EVM-PDK user's guide.