Attention to good layout practices is always
recommended. For best operational performance of the device, use good printed circuit board
(PCB) layout practices:
- To avoid converting common-mode signals
into differential signals and thermal electromotive forces (EMFs), make sure that both
input paths are symmetrical and well-matched for source impedance and capacitance.
- As shown in Figure 9-14, keep the external gain resistor close to the RG pins to keep the loop inductance as
low as possible and to avoid a potential parasitic coupling path. Even slight mismatch
in parasitic capacitance at the gain setting pins can degrade CMRR over frequency. In
applications that implement gain switching using switches or PhotoMOS® relays to
change the value of RG, select the component so that the switch capacitance
is as small as possible, and most importantly, so that capacitance mismatch between the
RG pins is minimized.
- Noise can propagate into analog
circuitry through the power pins of the device and of the circuit as a whole. Bypass
capacitors reduce the coupled noise by providing low-impedance power sources local to
the analog circuitry.
- Connect low-ESR, 0.1-µF ceramic
bypass capacitors between each supply pin and ground, placed as close as possible to
the device. A single bypass capacitor from V+ to ground is applicable for
single-supply applications.
- To reduce parasitic coupling, run the
input traces as far away as possible from the supply or output traces. If these traces
cannot be kept separate, crossing the sensitive trace perpendicular to the noisy trace
is much better than in parallel.
- Leakage on the FDA_IN+ and FDA_IN– pins can cause in a dc offset
error in the output voltages. Additionally, excessive parasitic capacitance at these
pins can result in decreased phase margin and affect the stability of the output stage.
If these pins are not used to implement deliberate capacitive feedback, follow best
practices to minimize leakage and parasitic capacitance. Consider implementing
keep-out areas in any ground planes that lie immediately below the pins.
- Minimize the number of thermal junctions. Ideally, the signal path
is routed within a single layer without vias.
- Keep sufficient distance from major
thermal energy sources (circuits with high power dissipation). If not possible, place
the device so that the effects of the thermal energy source on the high and low sides of
the differential signal path are evenly matched.
- Solder the thermal pad to the PCB. For the INA851 to properly
dissipate heat, connect the thermal pad to a plane or large copper pour that is
electrically connected to VS–, even for low-power applications.
- Keep the traces as short as
possible.