The inter-integrated circuit (I²C) bus is a single-ended, multi-controller, 2-wire bus for efficient inter-IC communication in half-duplex mode.

I²C uses open-drain technology, requiring two lines, serial data (SDA) and serial clock (SCL), to be connected to VDD by resistors (see Figure 8-1). Pulling the line to ground is considered a logic zero while letting the line float is a logic one. This logic is used as a channel access method. Transitions of logic states must occur while the SCL pin is low. Transitions while the SCL pin is high indicate START and STOP conditions. Typical supply voltages are 3.3 V and 5 V, although systems with higher or lower voltages are allowed.

I²C communication uses a 7-bit address space with 16 reserved addresses, so a theoretical maximum of 112 nodes can communicate on the same bus. In praxis, however, the number of nodes is limited by the specified, total bus capacitance of 400 pF, which restricts communication distances to a few meters.

The specified signaling rates for the ISO1540-Q1 and ISO1541-Q1 devices are 100 kbps (standard mode), 400 kbps (fast mode), 1 Mbps (fast mode plus).

The bus has two roles for nodes: controller and target. A controller node issues the clock and target addresses, and also initiates and ends data transactions. A target node receives the clock and addresses and responds to requests from the controller. Figure 8-2 shows a typical data transfer between controller and target.

Figure 8-2 Timing Diagram of a Complete Data Transfer

The controller initiates a transaction by creating a START condition, following by the 7-bit address of the target it wishes to communicate with. This is followed by a single read and write (R/W) bit, representing whether the controller wishes to write to 0, or to read from 1 the target. The controller then releases the SDA line to allow the target to acknowledge the receipt of data.

The target responds with an acknowledge bit (ACK) by pulling the SDA pin low during the entire high time of the 9th clock pulse on the SCL signal, after which the controller continues in either transmit or receive mode (according to the R/W bit sent), while the target continues in the complementary mode (receive or transmit, respectively).

The address and the 8-bit data bytes are sent most significant bit (MSB) first. The START bit is indicated by a high-to-low transition of SDA while SCL is high. The STOP condition is created by a low-to-high transition of SDA while SCL is high.

If the controller writes to a target, it repeatedly sends a byte with the target sending an ACK bit. In this case, the controller is in controller-transmit mode and the target is in target-receive mode.

If the controller reads from a target, it repeatedly receives a byte from the target, while acknowledging (ACK) the receipt of every byte but the last one (see Figure 8-3). In this situation, the controller is in controller-receive mode and the target is in target-transmit mode.

The controller ends the transmission with a STOP bit, or may send another START bit to maintain bus control for further transfers.

Figure 8-3 Transmit or Receive Mode Changes During a Data Transfer

When writing to a target, a controller mainly operates in transmit-mode and only changes to receive-mode when receiving acknowledgment from the target.

When reading from a target, the controller starts in transmit-mode and then changes to receive-mode after sending a READ request (R/W bit = 1) to the target. The target continues in the complementary mode until the end of a transaction.