Although the ISO1640-Q1 features bidirectional data channels, the device performs optimally when side 1 (SDA1 and SCL1) is connected to a single controller or node of an I2C network while side 2 (SDA2 and SCL2) is connected to the I2C bus. The maximum load permissible on the input lines, SDA1 and SCL1, is ≤ 80 pF and on the output lines, SDA2 and SCL2, is ≤ 400 pF. In addition to the bidirectional data and clock channels for the I2C network, the ISO1644 includes 3 GPIOs which can be used for static I/O lines or for a 3 wire SPI interface. These lines are designed to support up to 50 Mbps data transfer rate.

The power-supply capacitor with a value of 0.1-µF must be placed as close to the power supply pins as possible. The recommended placement of the capacitors must be 2-mm maximum from input and output power supply pins (VCC1 and VCC2).

The minimum pullup resistors on the input lines, SDA1 and SCL1 to VCC1 must be selected in such a way that input current drawn is ≤ 3.5 mA. The minimum pullup resistors on the input lines, SDA2 and SCL2, to VCC2 must be selected in such a way that output current drawn is ≤ 50 mA. The maximum pullup resistors on the bus lines (SDA1 and SCL1) to VCC1 and on bus lines (SDA2 and SCL2) to VCC2, depends on the load and rise time requirements on the respective lines to comply with I2C protocols. For more information, see I2C Bus Pullup Resistor Calculation.

The output waveforms for SDA1 and SCL1 are captured on the oscilloscope focusing on the low V_OL1 voltage offset offered with the ISO164x-Q1. This voltage offset is due to the output low level on side 1 designed to prevent a latch-up state mentioned in Section 8.5.

Figure 9-6 Typical ISO1640-Q1 Circuit Hookup