9.1 Overview

The isolator in Figure 17 is based on a capacitive isolation-barrier technique. The I/O channel of the device consists of two internal data channels, a high-frequency channel (HF) with a bandwidth from 100 kbps up to 150 Mbps, and a low-frequency channel (LF) covering the range from 100 kbps down to DC. In principle, a single-ended input signal entering the HF-channel is split into a differential signal through the inverter gate at the input. The following capacitor-resistor networks differentiate the signal into transients, which then are converted into differential pulses by two comparators. The comparator outputs drive a NOR-gate flip-flop the output of which feeds an output multiplexer. A decision logic (DCL) at the driving output of the flip-flop measures the durations between signal transients. If the duration between two consecutive transients exceeds a certain time limit, as in the case of a low-frequency signal, the DCL forces the output-multiplexer to switch from the high- to the low-frequency channel.

Because low-frequency input signals require the internal capacitors to assume prohibitively large values, these signals are pulse-width modulated (PWM) with the carrier frequency of an internal oscillator, thus creating a sufficiently high frequency signal, capable of passing the capacitive barrier. As the input is modulated, a low-pass filter (LPF) is required to remove the high-frequency carrier from the actual data before passing it on to the output multiplexer.

9.2 Functional Block Diagram

Figure 17. Conceptual Block Diagram of a Digital Capacitive Isolator

9.3 Feature Description

The ISO724xx family of devices is available in multiple channel configurations and default output-state options to enable wide variety of application uses. Table 1 lists these device features.

9.4 Device Functional Modes

Table 2 lists the ISO724xx functional modes. Table 3 lists the ISO7240CF functional modes.

9.4.1 Device I/O Schematics

Figure 18. Device I/O Schematics