SLLS984I June   2009  – July 2015 ISO7420 , ISO7420M , ISO7421

UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics: VCC1 and VCC2 at 5 V ±5%
    6. 6.6  Electrical Characteristics: VCC1 at 5 V ±5%, VCC2 at 3.3 V ±5%
    7. 6.7  Electrical Characteristics: VCC1 at 3.3 V ±5%, VCC2 at 5 V ±5%
    8. 6.8  Electrical Characteristics: VCC1 and VCC2 at 3.3 V ±5%
    9. 6.9  Power Dissipation Characteristics
    10. 6.10 Switching Characteristics: VCC1 and VCC2 at 5 V ±5%
    11. 6.11 Switching Characteristics: VCC1 at 5 V ±5%, VCC2 at 3.3 V ±5%
    12. 6.12 Switching Characteristics: VCC1 at 3.3 V ±5%, VCC2 at 5 V ±5%
    13. 6.13 Switching Characteristics: VCC1 and VCC2 at 3.3 V ±5%
    14. 6.14 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Insulation Characteristics
      2. 8.3.2 Package Characteristics
      3. 8.3.3 Safety Limiting Values
      4. 8.3.4 Regulatory Information
    4. 8.4 Device Functional Modes
      1. 8.4.1 Device I/O Schematics
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 PCB Material
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Related Links
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

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8 Detailed Description

8.1 Overview

The isolator in Figure 9 is based on a capacitive isolation barrier technique. The I/O channel of the device consists of two internal data channels, a high-frequency channel (HF) with a bandwidth from 100 kbps up to 1 Mbps, and a low-frequency channel (LF) covering the range from 100 kbps down to DC. In principle, a single- ended input signal entering the HF-channel is split into a differential signal via the inverter gate at the input. The following capacitor-resistor networks differentiate the signal into transients, which then are converted into differential pulses by two comparators. The comparator outputs drive a NOR-gate flip-flop whose output feeds an output multiplexer. A decision logic (DCL) at the driving output of the flip-flop measures the durations between signal transients. If the duration between two consecutive transients exceeds a certain time limit, (as in the case of a low-frequency signal), the DCL forces the output-multiplexer to switch from the high- to the low-frequency channel.

Because low-frequency input signals require the internal capacitors to assume prohibitively large values, these signals are pulse-width modulated (PWM) with the carrier frequency of an internal oscillator, thus creating a sufficiently high frequency signal, capable of passing the capacitive barrier. As the input is modulated, a low-pass filter (LPF) is needed to remove the high-frequency carrier from the actual data before passing it on to the output multiplexer.

8.2 Functional Block Diagram

ISO7420 ISO7420M ISO7421 fbdc_slls984.pngFigure 9. Conceptual Block Diagram of a Digital Capacitive Isolator

8.3 Feature Description

8.3.1 Insulation Characteristics

over recommended operating conditions (unless otherwise noted)
PARAMETER(1) TEST CONDITIONS SPECIFICATION UNIT
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12
VIORM Maximum working insulation voltage 566 VPK
VPR Input-to-output test voltage t = 1 s (100% production), partial discharge 5 pC 1062 VPK
VIOTM Transient overvoltage t = 60 s (qualification) 4242 VPK
t = 1 s (100% production)
RS Insulation resistance VIO = 500 V at TS >109 Ω
Pollution degree 2
UL 1577
VISO Isolation voltage per UL VTEST = VISO = 2500 VRMS, t = 60 s (qualification)
VTEST = 1.2 x VISO = 3000 VRMS, t = 1 s (100% production)		 2500 VRMS
(1) Climatic Classification 40/125/21

Table 1. IEC 60664-1 Ratings Table

PARAMETER TEST CONDITIONS SPECIFICATION
Material group II
Installation classification Rated mains voltage ≤ 150 VRMS I–IV
Rated mains voltage ≤ 300 VRMS I–III

8.3.2 Package Characteristics

over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
L(I01) Minimum air gap (clearance) Shortest terminal-to-terminal distance through air 4 mm
L(I02) Minimum external tracking (creepage) Shortest terminal-to-terminal distance across the package surface 4 mm
CTI Tracking resistance (comparative tracking index) DIN EN 60112 (VDE 0303-11); IEC 60112 >400 V
DTI Distance through the insulation Minimum internal gap (internal clearance) 0.014 mm
RIO Isolation resistance, input to output(1) VIO = 500 V, TA = 25°C >1012 Ω
VIO = 500 V, 100°C ≤ TA ≤ max >1011 Ω
CIO Barrier capacitance, input to output(1) VIO = 0.4 sin (2πft), f = 1 MHz 1 pF
CI Input capacitance(2) VI = VCC/2 + 0.4 sin (2πft), f = 1 MHz, VCC = 5 V 1 pF
(1) All pins on each side of the barrier tied together creating a two-terminal device.
(2) Measured from input pin to ground.

SPACER

NOTE

Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed-circuit board do not reduce this distance.

Creepage and clearance on a printed-circuit board become equal in certain cases. Techniques such as inserting grooves and/or ribs on a printed circuit board are used to help increase these specifications.

8.3.3 Safety Limiting Values

Safety limiting intends to prevent potential damage to the isolation barrier upon failure of input or output circuitry. A failure of the I/O can allow low resistance to ground or the supply and, without current limiting, dissipate sufficient power to overheat the die and damage the isolation barrier, potentially leading to secondary system failures.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
IS Safety input, output, or supply current θJA = 212°C/W, VI = 5.25 V, TJ = 150°C, TA = 25°C 112 mA
θJA = 212°C/W, VI = 3.45 V, TJ = 150°C, TA = 25°C 171
TS Maximum safety temperature 150 °C

The safety-limiting constraint is the absolute-maximum junction temperature specified in the Absolute Maximum Ratings table. The power dissipation and junction-to-air thermal impedance of the device installed in the application hardware determines the junction temperature. The assumed junction-to-air thermal resistance in the Thermal Information table is that of a device installed in the JESD51-3, Low-Effective-Thermal-Conductivity Test Board for Leaded Surface-Mount Packages and is conservative. The power is the recommended maximum input voltage times the current. The junction temperature is then the ambient temperature plus the power times the junction-to-air thermal resistance.

ISO7420 ISO7420M ISO7421 g002_C_lls984.gifFigure 10. θJC Thermal Derating Curve per VDE

8.3.4 Regulatory Information

VDE CSA UL CQC
Certified according to
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 and
DIN EN 61010-1 (VDE 0411-1): 2011-07		 Approved under CSA Component Acceptance Notice #5A Recognized under UL1577 Component Recognition Program(1) Certified according to GB4943.1-2011
Basic Insulation
Maximum Transient Overvoltage, 4242 VPK
Maximum Working Voltage, 566 VPK		 Basic insulation per CSA 60950-1-07 and IEC 60950-1 (2nd Ed),
390 VRMS maximum working voltage		 Single Protection, 2500 VRMS Basic Insulation, Altitude ≤ 5000 m, Tropical Climate, 250 VRMS maximum working voltage
Certificate number: 40016131 Master contract number: 220991 File number: E181974 Certificate number: CQC14001109540
(1) Production tested ≥ 3000 VRMS for 1 second in accordance with UL 1577.

8.4 Device Functional Modes

Table 2. Function Table(1)

VCCI VCCO INPUT
INA, INB		 OUTPUT
OUTA, OUTB
PU PU H H
L L
Open H(2)
PD PU X H(2)
X PD X Undetermined
(1) VCCI = Input-side power supply; VCCO = Output-side power supply; PU = Powered up (VCC ≥ 3.15 V); PD = Powered down (VCC ≤ 2.1 V); X = Irrelevant; H = High level; L = Low level
(2) In fail-safe condition, output defaults to high level.

8.4.1 Device I/O Schematics

ISO7420 ISO7420M ISO7421 IO_sch_lls984.gifFigure 11. Device I/O Schematics
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