SLLSE39E June   2010  – May 2015 ISO7520C , ISO7521C

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics: VCC1 and VCC2 at 5 V ± 5%
    6. 6.6  Electrical Characteristics: VCC1 at 5 V ± 5%, VCC2 at 3.3 V ± 5%
    7. 6.7  Electrical Characteristics: VCC1 at 3.3 V ± 5%, VCC2 at 5 V ± 5%
    8. 6.8  Electrical Characteristics: VCC1 and VCC2 at 3.3 V ± 5%
    9. 6.9  Switching Characteristics: VCC1 and VCC2 at 5 V ± 5%
    10. 6.10 Switching Characteristics: VCC1 at 5 V ± 5%, VCC2 at 3.3 V ± 5%
    11. 6.11 Switching Characteristics: VCC1 at 3.3 V ± 5%, VCC2 at 5 V ± 5%
    12. 6.12 Switching Characteristics: VCC1 and VCC2 at 3.3 V ± 5%
    13. 6.13 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Insulation Characteristics
      2. 8.3.2 IEC 60664-1 Ratings Table
      3. 8.3.3 Package Insulation and Safety-Related Specifications
      4. 8.3.4 Safety Limiting Values
      5. 8.3.5 Regulatory Information
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 PCB Material
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Related Links
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

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8 Detailed Description

8.1 Overview

The isolator in Figure 7 is based on a capacitive isolation barrier technique. The I/O channel of the device consists of two internal data channels, a high-frequency channel (HF) with a bandwidth from 100 kbps up to 1 Mbps, and a low-frequency channel (LF) covering the range from 100 kbps down to DC. In principle, a single- ended input signal entering the HF-channel is split into a differential signal through the inverter gate at the input. The following capacitor-resistor networks differentiate the signal into transients, which then are converted into differential pulses by two comparators. The comparator outputs drive a NOR-gate flip-flop whose output feeds an output multiplexer. A decision logic (DCL) at the driving output of the flip-flop measures the durations between signal transients. If the duration between two consecutive transients exceeds a certain time limit, (as in the case of a low-frequency signal), the DCL forces the output-multiplexer to switch from the high- to the low frequency channel. Because low-frequency input signals require the internal capacitors to assume prohibitively large values, these signals are pulse-width modulated (PWM) with the carrier frequency of an internal oscillator, thus creating a sufficiently high frequency signal, capable of passing the capacitive barrier. As the input is modulated, a low-pass filter (LPF) is needed to remove the high-frequency carrier from the actual data before passing it on to the output multiplexer.

8.2 Functional Block Diagram

ISO7520C ISO7521C FBD_E39_LLSE39.gifFigure 7. Conceptual Block Diagram of a Digital Capacitive Isolator

8.3 Feature Description

8.3.1 Insulation Characteristics

over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS SPECIFICATION UNIT
VIORM Maximum repetitive peak isolation voltage 1414 VPEAK
VPR Input to output test voltage Method a, After environmental tests subgroup 1,
VPR = VIORM x 1.6, t = 10 s,
Partial discharge < 5 pC		 2262 VPEAK
Method b1,
VPR = VIORM x 1.875, t = 1 s (100% Production test)
Partial discharge < 5 pC		 2651
After Input/Output Safety Test Subgroup 2/3,
VPR = VIORM x 1.2, t = 10 s,
Partial discharge < 5 pC		 1697
VIOTM Maximum Transient Isolation voltage
t = 60 sec (qualification)
6000 VPEAK
VISO Withstanding Isolation voltage per UL 1577 VTEST = VISO = 4243 VRMS, t = 60 sec (qualification);
VTEST = 1.2 × VISO = 5092 VRMS, t = 1 sec (100% production)		 4243 VRMS
RS Isolation resistance VIO = 500 V at TS = 150°C >109 Ω
Pollution degree 2

8.3.2 IEC 60664-1 Ratings Table

PARAMETER TEST CONDITIONS SPECIFICATION
Basic Isolation Group Material Group II
Installation Classification Rated mains voltages <= 150 Vrms I - IV
Rated mains voltages <= 600 Vrms I - III
Rated mains voltages <= 1000 Vrms I - II

8.3.3 Package Insulation and Safety-Related Specifications

over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
L(I01) Minimum air gap (Clearance) Shortest terminal-to-terminal distance through air 8.34 mm
L(I02) Minimum external tracking (Creepage) Shortest terminal-to-terminal distance across the package surface 8.1 mm
CTI Tracking resistance (Comparative Tracking Index) DIN EN 60112 (VDE 0303-11); IEC 60112 >400 V
Minimum internal gap (Internal Clearance) Distance through the insulation 0.014 mm
RIO Isolation resistance, input to output(1) VIO = 500 V, TA = 25ºC >1012 Ω
VIO = 500 V, 100ºC ≤ TA ≤ TA max >1011
CIO Barrier capacitance input to output(1) VIO = 0.4 sin(2πft), f = 1 MHz 2 pF
CI Input capacitance to ground(2) VI = VCC/2 + 0.4 sin(2πft), f = 1 MHz, VCC = 5 V 2 pF
(1) All pins on each side of the barrier tied together creating a 2-terminal device.
(2) Measured from input pin to ground.

NOTE

Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed-circuit-board (PCB) do not reduce this distance.

Creepage and clearance on a PCB become equal according to the measurement techniques shown in the Isolation Glossary. Techniques such as inserting grooves and/or ribs on a printed circuit board are used to help increase these specifications.

8.3.4 Safety Limiting Values

Safety limiting intends to prevent potential damage to the isolation barrier upon failure of input or output circuitry. A failure of the I/O can allow low resistance to ground or the supply and, without current-limiting, dissipate sufficient power to overheat the die and damage the isolation barrier potentially leading to secondary system failures.

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Is Safety input, output, or supply current θJA =79.9°C/W, VI = 5.25 V, TJ = 150°C, TA = 25°C 298 mA
θJA =79.9°C/W, VI = 3.45 V, TJ = 150°C, TA = 25°C 453
Ts Maximum Case Temperature 150 °C

The safety-limiting constraint is the absolute maximum junction temperature specified in the absolute maximum ratings table. The power dissipation and junction-to-air thermal impedance of the device installed in the application hardware determines the junction temperature. The assumed junction-to-air thermal resistance in the Thermal Information table is that of a device installed on a High-K Test Board for Leaded Surface-Mount Packages. The power is the recommended maximum input voltage times the current. The junction temperature is then the ambient temperature plus the power times the junction-to-air thermal resistance.

ISO7520C ISO7521C IEC_lilit_llse39.gifFigure 8. DW-16 RΘJC Thermal Derating Curve for VDE

8.3.5 Regulatory Information

VDE TUV CSA UL CQC
Certified according to DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 and DIN EN 61010-1 (VDE 0411-1):2011-07 Certified according to EN 60950-1 and EN 61010-1 Approved under CSA Component Acceptance Notice 5A, IEC 60950-1, IEC 61010-1, and IEC 60601-1 Recognized under 1577 Component Recognition Program Certified according to GB 4943.1-2011
Basic Insulation
Maximum Transient Isolation voltage, 6000 VPK
Maximum Repetitive Peak Isolation Voltage, 1414 VPK		 5000 VRMS Isolation Rating;
Reinforced Insulation, 400 VRMS maximum working voltage;
Basic Insulation, 600 VRMS maximum working voltage		 5000 VRMS Isolation Rating;
Reinforced insulation per CSA 60950-1-07+A1 and IEC 60950-1 2nd Ed.+A1, 380 VRMS max working voltage;
Reinforced insulation per CSA 61010-1-04 and IEC 61010-1 2nd Ed, 300 VRMS max working voltage;
2 Means of Patient Protection at 125 VRMS per IEC 60601-1 (3rd Ed.)		 Single Protection, 4243 VRMS Withstanding Isolation Voltage Reinforced Insulation, Altitude ≤ 5000 m, Tropical Climate, 250 VRMS maximum working voltage
Certificate Number: 40016131 Certificate Number: U8V 1309 77311 010 Master Contract Number: 220991 File Number: E181974 Certificate Number: CQC14001109542

8.4 Device Functional Modes

Table 1. Device Function Table

VCCI(1) VCCO(1) INPUT (INA, INB)(1) OUTPUT (OUTA, OUTB)(1)
PU PU H H
L L
Open H
PD PU X H
X PD X Undetermined
(1) VCCI = Input-side VCC; VCCO = Output-side VCC; PU = Powered Up (Vcc ≥ 3.15 V); PD = Powered Down (Vcc ≤ 2.1 V); X = Irrelevant; H = High Level; L = Low Level
ISO7520C ISO7521C IO_sch_llse39.gifFigure 9. Equivalent Input and Output Schematic Diagrams
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