米6体育平台手机版

ZHCSDV2 July 2015 ISO7820

PRODUCTION DATA.

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DWW|16
DW|16

散热焊盘机械数据 (封装 | 引脚)

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zhcsdv2_oa

6 Specifications

6.1 Absolute Maximum Ratings⁽¹⁾

		MIN	MAX	UNIT
Supply voltage⁽²⁾	V_CC1, V_CC2	–0.5	6	V
Voltage	INx, OUTx	–0.5	V_CC + 0.5⁽³⁾	V
Output Current	I_O	-15	15	mA
Surge Immunity			12.8	kV
Maximum junction temperature, T_J			150	°C
Storage temperature, T_stg		–65	150	°C

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltage values except differential I/O bus voltages are with respect to the local ground terminal (GND1 or GND2) and are peak voltage values.

(3) Maximum voltage must not exceed 6 V.

6.2 ESD Ratings

			VALUE	UNIT
V_ESD	Electrostatic discharge	Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins ⁽¹⁾	±6000	V
V_ESD	Electrostatic discharge	Charged device model (CDM), per JEDEC specification JESD22-C101, all pins⁽²⁾	±1500	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

			MIN	TYP	MAX	UNIT
V_CC1, V_CC2	Supply voltage		2.25		5.5	V
I_OH	High-level output current	V_CCO⁽²⁾ = 5 V	-4			mA
		V_CCO = 3.3 V	-2
		V_CCO = 2.5 V	-1
I_OL	Low-level output current	V_CCO = 5 V			4	mA
		V_CCO = 3.3 V			2
		V_CCO = 2.5 V			1
V_IH	High-level input voltage		0.7 x V_CC_I⁽²⁾		V_CCI	V
V_IL	Low-level input voltage		0		0.3 x V_CCI	V
DR	Signaling rate		0		100	Mbps
T_J	Junction temperature⁽¹⁾		-55		150	°C
T_A	Ambient temperature		-55	25	125	°C

(1) To maintain the recommended operating conditions for T_J, see the Thermal Information table.

(2) V_CCI = Input-side V_CC; V_CCO = Output-side V_CC.

6.4 Thermal Information

THERMAL METRIC		DW (16 Pins)	UNIT
R_θJA	Junction-to-ambient thermal resistance	84.7	°C/W
R_θJC(top)	Junction-to-case(top) thermal resistance	47.3
R_θJB	Junction-to-board thermal resistance	49.4
ψ_JT	Junction-to-top characterization parameter	19.1
ψ_JB	Junction-to-board characterization parameter	48.8
R_θJC(bottom)	Junction-to-case(bottom) thermal resistance	n/a

6.5 Power Rating

			VALUE	UNIT
P_D	Maximum power dissipation by ISO7820	V_CC1 = V_CC2 = 5.5 V, T_J = 150°C, C_L = 15 pF, input a 50 MHz 50% duty cycle square wave	100	mW
P_D1	Maximum power dissipation by side-1 of ISO7820		20
P_D2	Maximum power dissipation by side-2 of ISO7820		80

6.6 Electrical Characteristics, 5 V

V_CC1 = V_CC2 = 5 V ± 10% (over recommended operating conditions unless otherwise noted)

PARAMETER		TEST CONDITIONS		MIN	TYP	MAX	UNIT
V_OH	High-level output voltage	I_OH = –4 mA; see Figure 7		V_CCx⁽¹⁾ – 0.4	V_CCx – 0.2		V
V_OL	Low-level output voltage	I_OL = 4 mA; see Figure 7			0.2	0.4	V
V_I(HYS)	Input threshold voltage hysteresis			0.1 x V_CCx⁽¹⁾			V
I_IH	High-level input current	V_IH = V_CCx⁽¹⁾ at INx				10	μA
I_IL	Low-level input current	V_IL = 0 V at INx		-10			μA
CMTI	Common-mode transient immunity	V_I = V_CCx⁽¹⁾ or 0 V; see Figure 9		70	100		kV/μs
I_CC1	Supply current, DC Signal	DC signal: V_I = 0 V (Devices with suffix F) , V_I = V_CCI(Devices without suffix F)			0.9	1.3	mA
I_CC2	Supply current, DC Signal				1.2	1.8
I_CC1	Supply current, DC Signal	DC signal: V_I = V_CCI (Devices with suffix F) , V_I = 0 V(Devices without suffix F)			3.2	4.6
I_CC2	Supply current, DC Signal				1.3	2
I_CC1	Supply current	1 Mbps	AC Signal: All channels switching with square wave clock input; C_L = 15 pF		2.1	3
I_CC2	Supply current	1 Mbps			1.3	2
I_CC1	Supply current	10 Mbps			2.1	3
I_CC2	Supply current	10 Mbps			2.3	3.8
I_CC1	Supply current	100 Mbps			2.7	3.3
I_CC2	Supply current	100 Mbps			11.9	15.3

(1) V_CCI = Input-side V_CC; V_CCO = Output-side V_CC.

6.7 Electrical Characteristics, 3.3 V

V_CC1 = V_CC2 = 3.3 V ± 10% (over recommended operating conditions unless otherwise noted)

PARAMETER		TEST CONDITIONS		MIN	TYP	MAX	UNIT
V_OH	High-level output voltage	I_OH = –2 mA; see Figure 7		V_CCx⁽¹⁾ – 0.4	V_CCx – 0.2		V
V_OL	Low-level output voltage	I_OL = 2 mA; see Figure 7			0.2	0.4	V
V_I(HYS)	Input threshold voltage hysteresis			0.1 x V_CCx⁽¹⁾			V
I_IH	High-level input current	V_IH = V_CCx⁽¹⁾ at INx				10	μA
I_IL	Low-level input current	V_IL = 0 V at INx		-10			μA
CMTI	Common-mode transient immunity	V_I = V_CCx⁽¹⁾ or 0 V; see Figure 9		70	100		kV/μs
I_CC1	Supply current, DC Signal	DC signal: V_I = 0 V (Devices with suffix F) , V_I = V_CCI(Devices without suffix F)			0.9	1.3	mA
I_CC2	Supply current, DC Signal				1.2	1.8
I_CC1	Supply current, DC Signal	DC signal: V_I = V_CCI (Devices with suffix F) , V_I = 0 V(Devices without suffix F)			3.2	4.6
I_CC2	Supply current, DC Signal				1.3	2
I_CC1	Supply current	1 Mbps	AC Signal: All channels switching with square wave clock input; C_L = 15 pF		2.1	3
I_CC2	Supply current	1 Mbps			1.3	2
I_CC1	Supply current	10 Mbps			2.1	3
I_CC2	Supply current	10 Mbps			2.3	3.8
I_CC1	Supply current	100 Mbps			2.5	3.2
I_CC2	Supply current	100 Mbps			8.9	11.5

6.8 Electrical Characteristics, 2.5 V

V_CC1 = V_CC2 = 2.5 V ± 10% (over recommended operating conditions unless otherwise noted)

PARAMETER		TEST CONDITIONS		MIN	TYP	MAX	UNIT
V_OH	High-level output voltage	I_OH = –1 mA; see Figure 7		V_CCx⁽¹⁾ – 0.4	V_CCx – 0.2		V
V_OL	Low-level output voltage	I_OL = 1 mA; see Figure 7			0.2	0.4	V
V_I(HYS)	Input threshold voltage hysteresis			0.1 x V_CCx⁽¹⁾			V
I_IH	High-level input current	V_IH = V_CCx⁽¹⁾ at INx				10	μA
I_IL	Low-level input current	V_IL = 0 V at INx		-10			μA
CMTI	Common-mode transient immunity	V_I = V_CCx⁽¹⁾ or 0 V; see Figure 9		70	100		kV/μs
I_CC1	Supply current, DC Signal	DC signal: V_I = 0 V (Devices with suffix F) , V_I = V_CCI(Devices without suffix F)			0.9	1.3	mA
I_CC2	Supply current, DC Signal				1.2	1.8
I_CC1	Supply current, DC Signal	DC signal: V_I = V_CCI (Devices with suffix F) , V_I = 0 V(Devices without suffix F)			3.2	4.6
I_CC2	Supply current, DC Signal				1.3	2
I_CC1	Supply current	1 Mbps	AC Signal: All channels switching with square wave clock input; C_L = 15 pF		2.1	3
I_CC2	Supply current	1 Mbps			1.3	2
I_CC1	Supply current	10 Mbps			2.1	3
I_CC2	Supply current	10 Mbps			1.8	2.7
I_CC1	Supply current	100 Mbps			2.4	3.2
I_CC2	Supply current	100 Mbps			7	9.1

6.9 Switching Characteristics, 5 V

V_CC1 = V_CC2 = 5 V ± 10% (over recommended operating conditions unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
t_PLH, t_PHL	Propagation delay time	See Figure 7	6	10.7	16	ns
PWD⁽¹⁾	Pulse width distortion \|t_PHL – t_PLH\|	See Figure 7		0.6	4.6	ns
t_sk(pp)⁽²⁾	Part-to-part skew time				4.5	ns
t_r	Output signal rise time	See Figure 7		2.4	3.9	ns
t_f	Output signal fall time	See Figure 7		2.4	3.9	ns
t_fs	Default output delay time from input power loss	Measured from the time V_CC goes below 1.7 V. See Figure 8		0.2	9	μs
t_ie	Time interval error	2¹⁶- 1 PRBS data at 100 Mbps		1		ns

(1) Also known as Pulse Skew.

(2) t_sk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same direction while operating at identical supply voltages, temperature, input signals and loads.

6.10 Switching Characteristics, 3.3 V

V_CC1 = V_CC2 = 3.3 V ± 10% (over recommended operating conditions unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
t_PLH, t_PHL	Propagation delay time	See Figure 7	6	10.8	16	ns
PWD⁽¹⁾	Pulse width distortion \|t_PHL – t_PLH\|	See Figure 7		0.7	4.7	ns
t_sk(pp)⁽²⁾	Part-to-part skew time				4.5	ns
t_r	Output signal rise time	See Figure 7		1.3	3
t_f	Output signal fall time	See Figure 7		1.3	3
t_fs	Default output delay time from input power loss	Measured from the time V_CC goes below 1.7 V. See Figure 8		0.2	9	μs
t_ie	Time interval error	2¹⁶- 1 PRBS data at 100 Mbps		1		ns

(1) Also known as Pulse Skew.

6.11 Switching Characteristics, 2.5 V

V_CC1 = V_CC2 = 2.5 V ± 10% (over recommended operating conditions unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
t_PLH, t_PHL	Propagation delay time	See Figure 7	7.5	11.7	17.5	ns
PWD⁽¹⁾	Pulse width distortion \|t_PHL – t_PLH\|	See Figure 7		0.7	4.7	ns
t_sk(pp)⁽²⁾	Part-to-part skew time				4.5	ns
t_r	Output signal rise time	See Figure 7		1.8	3.5
t_f	Output signal fall time	See Figure 7		1.8	3.5
t_fs	Default output delay time from input power loss	Measured from the time V_CC goes below 1.7 V. See Figure 8		0.2	9	μs
t_ie	Time interval error	2¹⁶- 1 PRBS data at 100 Mbps		1		ns