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ZHCSFT4A March 2016 – August 2016 ISO7820LL , ISO7821LL

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9 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

9.1 Application Information

The ISO782xLL is a family of high-performance, reinforced isolated dual-LVDS buffers. Isolation can be used to help achieve human and system safety, to overcome ground potential difference (GPD), or to improve noise immunity and system performance.

The LVDS signaling can be used over most interfaces to achieve higher data rates because the LVDS is only a physical layer. LVDS can also be used for a proprietary communication scheme implemented between a host controller and a slave. Example use cases include connecting a high-speed I/O module to a host controller, a subsystem connecting to a backplane, and connection between two high-speed subsystems. Many of these systems operate under harsh environments making them susceptible to electromagnetic interferences, voltage surges, electrical fast transients (EFT), and other disturbances. These systems must also meet strict limits on radiated emissions. Using isolation in combination with a robust low-noise signaling standard such as LVDS, achieves both high immunity to noise and low emissions.

Example end applications that could benefit from the ISO782xLL family of devices include high-voltage motor control, test and measurement, industrial automation, and medical equipment.

9.2 Typical Application

One application for isolated LVDS buffers is for point-to-point communication between two high-speed capable, application-specific integrated circuits (ASICs) or FPGAs. In a high-voltage motor control application, for example, Node 1 could be a controller on a low-voltage or earth referenced board, and Node 2, could be controller placed on the power board, biased to high voltage. Figure 29 and Figure 30 show the application schematics.

Figure 30 provides further details of using the ISO782xLL family of devices to isolate the LVDS interface. The LVDS connection to the ISO782xLL family of devices can be traces on a board (shown as straight lines between Node 1 and the ISO782xLL device), a twisted pair cable (as shown between Node 2 and the ISO782xLL device), or any other controlled impedance channel. Differential 100-Ω terminations are placed near each LVDS receiver. The characteristic impedance of the channel should also be 100-Ω differential.

In the example shown in Figure 29 and Figure 30, the ISO782xLL family of devices provides reinforced or safety isolation between the high-voltage elements of the motor drive and the low-voltage control circuitry. This configuration also ensures reliable communication, regardless of the high conducted and radiated noise present in the system.

ISO7820LL ISO7821LL typ_app_motor_control_sllset8.gif

Figure 29. Isolated LVDS Interface in Motor Control Application

Figure 30. Isolated LVDS Interface Between Two Nodes (ASIC or FPGA)

9.2.1 Design Requirements

For the ISO782xLL family of devices, use the parameters listed in Table 2.

Table 2. Design Parameters

PARAMETER	VALUE
Supply voltage range, V_CC1 and V_CC2	2.25 V to 5.5 V
Receiver common-mode voltage range	For V_CCx ≥ 3 V: 0.5 \|V_ID\| to 2.4 – 0.5 \|V_ID\|
Receiver common-mode voltage range	For V_CCx < 3 V: 0.5 \|V_ID\| to V_CCx – 0.6 – 0.5 \|V_ID\|
External termination resistance	100 Ω
Interconnect differential characteristic impedance	100 Ω
Signaling rate	0 to 100 Mbps
Decoupling capacitor from V_CC1 and GND1	0.1 µF
Decoupling capacitor from V_CC2 and GND2	0.1 µF

9.2.2 Detailed Design Procedure

The ISO782xLL family of devices has minimum requirements on external components for correct operation. External bypass capacitors (0.1 µF) are required for both supplies (V_CC1 and V_CC2). A termination resistor with a value of 100 Ω is required between each differential input pair (INx+ and INx–), with the resistors placed as close to the device pins as possible. A differential termination resistor with a value of 100 Ω is required on the far end for the LVDS transmitters. Figure 31 and Figure 32 show these connections.

ISO7820LL ISO7821LL typ_app_hook-up_820_sllset8.gif

Figure 31. Typical ISO7820LL Circuit Hook-Up

ISO7820LL ISO7821LL typ_app_hook-up_821_sllset8.gif

Figure 32. Typical ISO7821LL Circuit Hook-Up

9.2.2.1 Electromagnetic Compatibility (EMC) Considerations

Many applications in harsh industrial environment are sensitive to disturbances such as electrostatic discharge (ESD), electrical fast transient (EFT), surge and electromagnetic emissions. These electromagnetic disturbances are regulated by international standards such as IEC 61000-4-x and CISPR 22. Although system-level performance and reliability depends, to a large extent, on the application board design and layout, the ISO782xLL family of devices incorporates many chip-level design improvements for overall system robustness. Some of these improvements include:

Robust ESD protection cells for input and output signal pins and inter-chip bond pads.
Low-resistance connectivity of ESD cells to supply and ground pins.
Enhanced performance of high voltage isolation capacitor for better tolerance of ESD, EFT and surge events.
Bigger on-chip decoupling capacitors to bypass undesirable high energy signals through a low impedance path.
PMOS and NMOS devices isolated from each other by using guard rings to avoid triggering of parasitic SCRs.
Reduced common mode currents across the isolation barrier by ensuring purely differential internal operation.

9.2.3 Application Curve

Figure 33 shows a typical eye diagram of the ISO782xLL family of devices which indicates low jitter and a wide-open eye at the maximum data rate of 100 Mbps.

ISO7820LL ISO7821LL eye_diagram_sllset8.png

Figure 33. Eye Diagram at 100 Mbps PRBS, 3.3 V and 25°C