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ZHCSE62A July 2015 – September 2015 ISO7831

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DWW|16
DW|16

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6 Specifications

6.1 Absolute Maximum Ratings

See ⁽¹⁾

			MIN	MAX	UNIT
V_CC1, V_CC2	Supply voltage⁽²⁾		–0.5	6	V
	Voltage	INx	–0.5	V_CCX + 0.5⁽³⁾	V
		OUTx
		ENx
I_O	Output current		–15	15	mA
T_stg	Storage temperature		–65	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltage values except differential I/O bus voltages are with respect to the local ground terminal (GND1 or GND2) and are peak voltage values.

(3) Maximum voltage must not exceed 6 V

6.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins⁽¹⁾	±6000	V
V_(ESD)	Electrostatic discharge	Charged device model (CDM), per JEDEC specification JESD22-C101, all pins⁽²⁾	±1500	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

			MIN	NOM	MAX	UNIT
V_CC1, V_CC2	Supply voltage		2.25		5.5	V
I_OH	High-level output current	V_CCO⁽²⁾ = 5 V	–4			mA
		V_CCO⁽²⁾ = 3.3 V	–2
		V_CCO⁽²⁾ = 2.5 V	–1
I_OL	Low-level output current	V_CCO⁽²⁾ = 5 V			4	mA
		V_CCO⁽²⁾ = 3.3 V			2
		V_CCO⁽²⁾ = 2.5 V			1
V_IH	High-level input voltage		0.7 × V_CCI ⁽²⁾		V_CCI ⁽²⁾	V
V_IL	Low-level input voltage		0		0.3 × V_CCI⁽²⁾	V
DR	Signaling rate		0		100	Mbps
T_J	Junction temperature⁽¹⁾		–55		150	°C
T_A	Ambient temperature		–55	25	125	°C

(1) To maintain the recommended operating conditions for T_J, see Thermal Information.

(2) V_CCI = Input-side V_CC; V_CCO = Output-side V_CC.

6.4 Thermal Information

THERMAL METRIC⁽¹⁾		DW (SOIC)	UNIT
THERMAL METRIC⁽¹⁾		16 Pins	UNIT
R_θJA	Junction-to-ambient thermal resistance	78.9	°C/W
R_θJC(top)	Junction-to-case(top) thermal resistance	41.6
R_θJB	Junction-to-board thermal resistance	43.6
ψ_JT	Junction-to-top characterization parameter	15.5
ψ_JB	Junction-to-board characterization parameter	43.1
R_θJC(bottom)	Junction-to-case(bottom) thermal resistance	N/A

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

6.5 Power Rating

			VALUE	UNIT
P_D	Maximum power dissipation by ISO7831	V_CC1 = V_CC2 = 5.5 V, T_J = 150°C, C_L = 15 pF, input a 50 MHz 50% duty cycle square wave	150	mW
P_D1	Maximum power dissipation by side-1 of ISO7831		50
P_D2	Maximum power dissipation by side-2 of ISO7831		100

6.6 Electrical Characteristics, 5 V

V_CC1 = V_CC2 = 5 V ±10% (over recommended operating conditions unless otherwise noted)

PARAMETER		TEST CONDITIONS		MIN	TYP	MAX	UNIT
V_OH	High-level output voltage	I_OH = –4 mA; see Figure 7		V_CCO⁽¹⁾ – 0.4	V_CCO⁽¹⁾ – 0.2		V
V_OL	Low-level output voltage	I_OL = 4 mA; see Figure 7			0.2	0.4	V
V_I(HYS)	Input threshold voltage hysteresis			0.1 × V_CCO⁽¹⁾			V
I_IH	High-level input current	V_IH = V_CCI⁽¹⁾ at INx or ENx				10	μA
I_IL	Low-level input current	V_IL = 0 V at INx or ENx		–10			μA
CMTI	Common-mode transient immunity	V_I = V_CCI⁽¹⁾ or 0 V; see Figure 10		70	100		kV/μs
I_CC1	Supply current	Disable; EN1 = EN2 = 0 V	DC signal: V_I = 0 V (Devices with suffix F) , V_I = V_CCI (Devices without suffix F)		1.0	1.6	mA
I_CC2		Disable; EN1 = EN2 = 0 V	DC signal: V_I = 0 V (Devices with suffix F) , V_I = V_CCI (Devices without suffix F)		0.8	1.3
I_CC1		Disable; EN1 = EN2 = 0 V	DC signal: V_I = V_CCI (Devices with suffix F) , V_I = 0 V(Devices without suffix F)		3.3	4.8
I_CC2		Disable; EN1 = EN2 = 0 V	DC signal: V_I = V_CCI (Devices with suffix F) , V_I = 0 V(Devices without suffix F)		2	2.9
I_CC1		DC signal	DC signal: V_I = 0 V (Devices with suffix F) , V_I = V_CCI (Devices without suffix F)		1.4	2.3
I_CC2		DC signal	DC signal: V_I = 0 V (Devices with suffix F) , V_I = V_CCI (Devices without suffix F)		1.7	2.6
I_CC1		DC signal	DC signal: V_I = V_CCI (Devices with suffix F) , V_I = 0 V(Devices without suffix F)		3.8	5.6
I_CC2		DC signal	DC signal: V_I = V_CCI (Devices with suffix F) , V_I = 0 V(Devices without suffix F)		3	4.3
I_CC1		1 Mbps	AC signal: All channels switching with square wave clock input; C_L = 15 pF		2.6	4
I_CC2		1 Mbps			2.4	3.6
I_CC1		10 Mbps			3.2	4.5
I_CC2		10 Mbps			3.4	4.6
I_CC1		100 Mbps			8.7	10.5
I_CC2		100 Mbps			13.2	15.8

(1) V_CCI = Input-side V_CC; V_CCO = Output-side V_CC.

6.7 Electrical Characteristics, 3.3 V

V_CC1 = V_CC2 = 3.3 V ±10% (over recommended operating conditions unless otherwise noted)

PARAMETER		TEST CONDITIONS		MIN	TYP	MAX	UNIT
V_OH	High-level output voltage	I_OH = –2 mA; see Figure 7		V_CCO⁽¹⁾ – 0.4	V_CCO⁽¹⁾ – 0.2		V
V_OL	Low-level output voltage	I_OL = 2 mA; see Figure 7			0.2	0.4	V
V_I(HYS)	Input threshold voltage hysteresis			0.1 × V_CCO⁽¹⁾			V
I_IH	High-level input current	V_IH = V_CCI⁽¹⁾ at INx or ENx				10	μA
I_IL	Low-level input current	V_IL = 0 V at INx or ENx		-10			μA
CMTI	Common-mode transient immunity	V_I = V_CCI⁽¹⁾ or 0 V; see Figure 10		70	100		kV/μs
I_CC1	Supply current	Disable; EN1 = EN2 = 0 V	DC signal: V_I = 0 V (Devices with suffix F) , V_I = V_CCI (Devices without suffix F)		1.0	1.6	mA
I_CC2		Disable; EN1 = EN2 = 0 V	DC signal: V_I = 0 V (Devices with suffix F) , V_I = V_CCI (Devices without suffix F)		0.8	1.3
I_CC1		Disable; EN1 = EN2 = 0 V	DC signal: V_I = V_CCI (Devices with suffix F) , V_I = 0 V(Devices without suffix F)		3.3	4.8
I_CC2		Disable; EN1 = EN2 = 0 V	DC signal: V_I = V_CCI (Devices with suffix F) , V_I = 0 V(Devices without suffix F)		1.9	2.9
I_CC1		DC signal	DC signal: V_I = 0 V (Devices with suffix F) , V_I = V_CCI (Devices without suffix F)		1.4	2.3
I_CC2		DC signal	DC signal: V_I = 0 V (Devices with suffix F) , V_I = V_CCI (Devices without suffix F)		1.7	2.6
I_CC1		DC signal	DC signal: V_I = V_CCI (Devices with suffix F) , V_I = 0 V(Devices without suffix F)		3.8	5.6
I_CC2		DC signal	DC signal: V_I = V_CCI (Devices with suffix F) , V_I = 0 V(Devices without suffix F)		2.9	4.3
I_CC1		1 Mbps	AC signal: All channels switching with square wave clock input; C_L = 15 pF		2.6	4
I_CC2		1 Mbps			2.4	3.5
I_CC1		10 Mbps			3.0	4.3
I_CC2		10 Mbps			3.1	4.3
I_CC1		100 Mbps			6.9	8.3
I_CC2		100 Mbps			10.1	12.2

(1) V_CCI = Input-side V_CC; V_CCO = Output-side V_CC.

6.8 Electrical Characteristics, 2.5 V

V_CC1 = V_CC2 = 2.5 V ±10% (over recommended operating conditions unless otherwise noted)

PARAMETER		TEST CONDITIONS		MIN	TYP	MAX	UNIT
V_OH	High-level output voltage	I_OH = –1 mA; see Figure 7		V_CCO⁽¹⁾ – 0.4	V_CCO⁽¹⁾ – 0.2		V
V_OL	Low-level output voltage	I_OL = 1 mA; see Figure 7			0.2	0.4	V
V_I(HYS)	Input threshold voltage hysteresis			0.1 × V_CCO⁽¹⁾			V
I_IH	High-level input current	V_IH = V_CCI⁽¹⁾ at INx or ENx				10	μA
I_IL	Low-level input current	V_IL = 0 V at INx or ENx		–10			μA
CMTI	Common-mode transient immunity	V_I = V_CCI⁽¹⁾ or 0 V; see Figure 10		70	100		kV/μs
I_CC1	Supply current	Disable; EN1 = EN2 = 0 V	DC signal: V_I = 0 V (Devices with suffix F) , V_I = V_CCI (Devices without suffix F)		0.9	1.6	mA
I_CC2		Disable; EN1 = EN2 = 0 V	DC signal: V_I = 0 V (Devices with suffix F) , V_I = V_CCI (Devices without suffix F)		0.8	1.3
I_CC1		Disable; EN1 = EN2 = 0 V	DC signal: V_I = V_CCI (Devices with suffix F) , V_I = 0 V(Devices without suffix F)		3.3	4.8
I_CC2		Disable; EN1 = EN2 = 0 V	DC signal: V_I = V_CCI (Devices with suffix F) , V_I = 0 V(Devices without suffix F)		1.9	2.9
I_CC1		DC signal	DC signal: V_I = 0 V (Devices with suffix F) , V_I = V_CCI (Devices without suffix F)		1.4	2.3
I_CC2		DC signal	DC signal: V_I = 0 V (Devices with suffix F) , V_I = V_CCI (Devices without suffix F)		1.7	2.6
I_CC1		DC signal	DC signal: V_I = V_CCI (Devices with suffix F) , V_I = 0 V(Devices without suffix F)		3.8	5.6
I_CC2		DC signal	DC signal: V_I = V_CCI (Devices with suffix F) , V_I = 0 V(Devices without suffix F)		2.9	4.3
I_CC1		1 Mbps	AC signal: All channels switching with square wave clock input; C_L = 15 pF		2.6	4
I_CC2		1 Mbps			2.3	3.5
I_CC1		10 Mbps			2.9	4.3
I_CC2		10 Mbps			2.9	4.1
I_CC1		100 Mbps			5.8	7.2
I_CC2		100 Mbps			8.2	10.0

(1) V_CCI = Input-side V_CC; V_CCO = Output-side V_CC.

6.9 Switching Characteristics, 5 V

V_CC1 = V_CC2 = 5 V ±10% (over recommended operating conditions unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
t_PLH, t_PHL	Propagation delay time	See Figure 7	6	11	16	ns
PWD⁽¹⁾	Pulse width distortion \|t_PHL – t_PLH\|	See Figure 7		0.55	4.1
t_sk(o) ⁽²⁾	Channel-to-channel output skew time	Same-direction channels			2.5
t_sk(pp) ⁽³⁾	Part-to-part skew time				4.5
t_r	Output signal rise time	See Figure 7		1.7	3.9
t_f	Output signal fall time	See Figure 7		1.9	3.9
t_PHZ	Disable propagation delay, high-to-high impedance output	See Figure 8		12	20
t_PLZ	Disable propagation delay, low-to-high impedance output			12	20
t_PZH	Enable propagation delay, high impedance-to-high output			10	20	ns
t_PZH	Enable propagation delay, high impedance-to-high output			2	2.5	μs
t_PZL	Enable propagation delay, high impedance-to-low output			2	2.5	μs
t_PZL	Enable propagation delay, high impedance-to-low output			10	20	ns
t_fs	Default output delay time from input power loss	Measured from the time V_CC goes below 1.7 V. See Figure 9		0.2	9	μs
t_ie	Time interval error	2¹⁶– 1 PRBS data at 100 Mbps		0.90		ns

(1) Also known as pulse skew.

(2) t_sk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same direction while driving identical loads.

(3) t_sk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same direction while operating at identical supply voltages, temperature, input signals and loads.

6.10 Switching Characteristics, 3.3 V

V_CC1 = V_CC2 = 3.3 V ±10% (over recommended operating conditions unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
t_PLH, t_PHL	Propagation delay time	See Figure 7	6	10.8	16	ns
PWD⁽¹⁾	Pulse width distortion \|t_PHL – t_PLH\|	See Figure 7		0.7	4.2
t_sk(o) ⁽²⁾	Channel-to-channel output skew time	Same-direction channels			2.2
t_sk(pp) ⁽³⁾	Part-to-part skew time				4.5
t_r	Output signal rise time	See Figure 7		0.8	3
t_f	Output signal fall time	See Figure 7		0.8	3
t_PHZ	Disable propagation delay, high-to-high impedance output	See Figure 8		17	32
t_PLZ	Disable propagation delay, low-to-high impedance output			17	32
t_PZH	Enable propagation delay, high impedance-to-high output			17	32	ns
t_PZH	Enable propagation delay, high impedance-to-high output			2	2.5	μs
t_PZL	Enable propagation delay, high impedance-to-low output			2	2.5	μs
t_PZL	Enable propagation delay, high impedance-to-low output			17	32	ns
t_fs	Default output delay time from input power loss	Measured from the time V_CC goes below 1.7 V. See Figure 9		0.2	9	μs
t_ie	Time interval error	2¹⁶– 1 PRBS data at 100 Mbps		0.91		ns

(1) Also known as Pulse Skew.

(2) t_sk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same direction while driving identical loads.

6.11 Switching Characteristics, 2.5 V

V_CC1 = V_CC2 = 2.5 V ±10% (over recommended operating conditions unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
t_PLH, t_PHL	Propagation delay time	See Figure 7	7.5	11.7	17.5	ns
PWD⁽¹⁾	Pulse width distortion \|t_PHL – t_PLH\|	See Figure 7		0.66	4.2
t_sk(o) ⁽²⁾	Channel-to-channel output skew time	Same-direction Channels			2.2
t_sk(pp) ⁽³⁾	Part-to-part skew time				4.5
t_r	Output signal rise time	See Figure 7		1	3.5
t_f	Output signal fall time	See Figure 7		1.2	3.5
t_PHZ	Disable propagation delay, high-to-high impedance output	See Figure 8		22	45
t_PLZ	Disable propagation delay, low-to-high impedance output			22	45
t_PZH	Enable propagation delay, high impedance-to-high output			18	45	ns
t_PZH	Enable propagation delay, high impedance-to-high output			2	2.5	μs
t_PZL	Enable propagation delay, high impedance-to-low output			2	2.5	μs
t_PZL	Enable propagation delay, high impedance-to-low output			18	45	ns
t_fs	Default output delay time from input power loss	Measured from the time V_CC goes below 1.7 V. See Figure 9		0.2	9	μs
t_ie	Time interval error	2¹⁶– 1 PRBS data at 100 Mbps		0.91		ns

(1) Also known as pulse skew.

(2) t_sk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same direction while driving identical loads.