The CAN bus has two logical states during operation: recessive and dominant. A dominant bus state occurs when the bus is driven differentially and corresponds to a logic low on the TXD and RXD pins. A recessive bus state occurs when the bus is biased to V_CC/2 via the high-resistance internal input resistors (R_IN) of the receiver and corresponds to a logic high on the TXD and RXD pins.

A dominant state overwrites the recessive state during arbitration. Multiple CAN nodes may be transmitting a dominant bit at the same time during arbitration, and in this case the differential voltage of the bus is greater than the differential voltage of a single driver.

The ISOW1044 transceiver implements a standby (STB ) mode which enables a third bus state where the bus pins are weakly biased to ground via the high resistance internal resistors of the receiver.

Figure 10-4 Bus States (Physical Bit Representation)

Figure 10-5 Simplified Recessive Common Mode Bias and Receiver