The ISOW774x-Q1 device has built-in UVLO on the V_IO, V_DD, and V_ISOIN supplies with positive-going and negative-going thresholds and hysteresis. Both the power converter supply (VDD) and logic supply (VIO) need to be present for the device to work. If either of them is below its UVLO, both the signal path and the power converter are disabled.

When the V_DD voltage crosses the positive-going UVLO threshold during power-up, the DC-DC converter initializes and the power converter duty cycle is increased in a controlled manner. This soft-start scheme limits primary peak currents drawn from the V_DD supply and charges the V_ISOOUT output in a controlled manner, avoiding overshoots. Outputs of the isolated data channels are in an indeterminate state until the V_IO or V_DD voltage crosses the positive-going UVLO threshold. When the UVLO positive-going threshold is crossed on the secondary side V_ISOOUT pin, the feedback data channel starts providing feedback to the primary controller. The regulation loop takes over and the isolated data channels go to the normal state defined by the respective input channels or their default states. Design should consider a sufficient time margin (typically 10 ms with 10-µF load capacitance) to allow this power up sequence before valid data channels are accounted for system functionality.

When either V_IO or V_DD power is lost, the primary side DC-DC controller turns off when the UVLO lower threshold is reached. The V_ISOOUT capacitor then discharges depending on the external load. The isolated data outputs on the V_ISOIN side are returned to the default state for the brief time that the V_ISOIN voltage takes to discharge to zero.