ZHCSHP9C May 2017 – October 2018 IWR1443
PRODUCTION DATA.
- 1器件概述
- 2修订历史记录
- 3Device Comparison
- 4Terminal Configuration and Functions
-
5Specifications
- 5.1 Absolute Maximum Ratings
- 5.2 ESD Ratings
- 5.3 Power-On Hours (POH)
- 5.4 Recommended Operating Conditions
- 5.5 Power Supply Specifications
- 5.6 Power Consumption Summary
- 5.7 RF Specification
- 5.8 Thermal Resistance Characteristics for FCBGA Package [ABL0161]
- 5.9
Timing and Switching Characteristics
- 5.9.1 Power Supply Sequencing and Reset Timing
- 5.9.2 Synchronized Frame Triggering
- 5.9.3 Input Clocks and Oscillators
- 5.9.4 Multibuffered / Standard Serial Peripheral Interface (MibSPI)
- 5.9.5 LVDS Interface Configuration
- 5.9.6 General-Purpose Input/Output
- 5.9.7 Controller Area Network Interface (DCAN)
- 5.9.8 Serial Communication Interface (SCI)
- 5.9.9 Inter-Integrated Circuit Interface (I2C)
- 5.9.10 Quad Serial Peripheral Interface (QSPI)
- 5.9.11 JTAG Interface
- 5.9.12 Camera Serial Interface (CSI)
- 6Detailed Description
- 7Applications, Implementation, and Layout
- 8Device and Documentation Support
- 9Mechanical, Packaging, and Orderable Information
5.9.5 LVDS Interface Configuration
The IWR1443 supports seven differential LVDS IOs/Lanes. The lane configuration supported is four Data lanes (LVDS_TXP/M), one Bit Clock lane (LVDS_CLKP/M) and one Frame clock lane (LVDS_FRCLKP/M), and one HS_DEBUG LVDS pair. The LVDS interface is used for debugging. The LVDS interface supports the following data rates:
- 900 Mbps (450 MHz DDR Clock)
- 600 Mbps (300 MHz DDR Clock)
- 450 Mbps (225 MHz DDR Clock)
- 400 Mbps (200 MHz DDR Clock)
- 300 Mbps (150 MHz DDR Clock)
- 225 Mbps (112.5 MHz DDR Clock)
- 150 Mbps (75 MHz DDR Clock)
Note that the bit clock is in DDR format and hence the numbers of toggles in the clock is equivalent to data.
Figure 5-12 LVDS Interface Lane Configuration And Relative Timings