ZHCSHP9C May 2017 – October 2018 IWR1443
PRODUCTION DATA.
- 1器件概述
- 2修订历史记录
- 3Device Comparison
- 4Terminal Configuration and Functions
-
5Specifications
- 5.1 Absolute Maximum Ratings
- 5.2 ESD Ratings
- 5.3 Power-On Hours (POH)
- 5.4 Recommended Operating Conditions
- 5.5 Power Supply Specifications
- 5.6 Power Consumption Summary
- 5.7 RF Specification
- 5.8 Thermal Resistance Characteristics for FCBGA Package [ABL0161]
- 5.9
Timing and Switching Characteristics
- 5.9.1 Power Supply Sequencing and Reset Timing
- 5.9.2 Synchronized Frame Triggering
- 5.9.3 Input Clocks and Oscillators
- 5.9.4 Multibuffered / Standard Serial Peripheral Interface (MibSPI)
- 5.9.5 LVDS Interface Configuration
- 5.9.6 General-Purpose Input/Output
- 5.9.7 Controller Area Network Interface (DCAN)
- 5.9.8 Serial Communication Interface (SCI)
- 5.9.9 Inter-Integrated Circuit Interface (I2C)
- 5.9.10 Quad Serial Peripheral Interface (QSPI)
- 5.9.11 JTAG Interface
- 5.9.12 Camera Serial Interface (CSI)
- 6Detailed Description
- 7Applications, Implementation, and Layout
- 8Device and Documentation Support
- 9Mechanical, Packaging, and Orderable Information
Table 5-16 I2C Timing Requirements(1)
| STANDARD MODE | FAST MODE | UNIT | ||||
|---|---|---|---|---|---|---|
| MIN | MAX | MIN | MAX | |||
| tc(SCL) | Cycle time, SCL | 10 | 2.5 | μs | ||
| tsu(SCLH-SDAL) | Setup time, SCL high before SDA low
(for a repeated START condition) |
4.7 | 0.6 | μs | ||
| th(SCLL-SDAL) | Hold time, SCL low after SDA low
(for a START and a repeated START condition) |
4 | 0.6 | μs | ||
| tw(SCLL) | Pulse duration, SCL low | 4.7 | 1.3 | μs | ||
| tw(SCLH) | Pulse duration, SCL high | 4 | 0.6 | μs | ||
| tsu(SDA-SCLH) | Setup time, SDA valid before SCL high | 250 | 100 | μs | ||
| th(SCLL-SDA) | Hold time, SDA valid after SCL low | 0 | 3.45(1) | 0 | 0.9 | μs |
| tw(SDAH) | Pulse duration, SDA high between STOP and START conditions | 4.7 | 1.3 | μs | ||
| tsu(SCLH-SDAH) | Setup time, SCL high before SDA high
(for STOP condition) |
4 | 0.6 | μs | ||
| tw(SP) | Pulse duration, spike (must be suppressed) | 0 | 50 | ns | ||
| Cb(2)(3) | Capacitive load for each bus line | 400 | 400 | pF | ||
(1) The I2C pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the device is powered down.
(2) The maximum th(SDA-SCLL) for I2C bus devices has only to be met if the device does not stretch the low period (tw(SCLL)) of the SCL signal.
(3) Cb = total capacitance of one bus line in pF. If mixed with fast-mode devices, faster fall-times are allowed.
Figure 5-14 I2C Timing Diagram NOTE
- A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL signal) to bridge the undefined region of the falling edge of SCL.
- The maximum th(SDA-SCLL) has only to be met if the device does not stretch the LOW period (tw(SCLL)) of the SCL signal. E.A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement tsu(SDA-SCLH) ≥ 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line tr max + tsu(SDA-SCLH).