ZHCSHP9C May 2017 – October 2018 IWR1443
PRODUCTION DATA.
- 1器件概述
- 2修订历史记录
- 3Device Comparison
- 4Terminal Configuration and Functions
-
5Specifications
- 5.1 Absolute Maximum Ratings
- 5.2 ESD Ratings
- 5.3 Power-On Hours (POH)
- 5.4 Recommended Operating Conditions
- 5.5 Power Supply Specifications
- 5.6 Power Consumption Summary
- 5.7 RF Specification
- 5.8 Thermal Resistance Characteristics for FCBGA Package [ABL0161]
- 5.9
Timing and Switching Characteristics
- 5.9.1 Power Supply Sequencing and Reset Timing
- 5.9.2 Synchronized Frame Triggering
- 5.9.3 Input Clocks and Oscillators
- 5.9.4 Multibuffered / Standard Serial Peripheral Interface (MibSPI)
- 5.9.5 LVDS Interface Configuration
- 5.9.6 General-Purpose Input/Output
- 5.9.7 Controller Area Network Interface (DCAN)
- 5.9.8 Serial Communication Interface (SCI)
- 5.9.9 Inter-Integrated Circuit Interface (I2C)
- 5.9.10 Quad Serial Peripheral Interface (QSPI)
- 5.9.11 JTAG Interface
- 5.9.12 Camera Serial Interface (CSI)
- 6Detailed Description
- 7Applications, Implementation, and Layout
- 8Device and Documentation Support
- 9Mechanical, Packaging, and Orderable Information
6.4.1.1 Clock Subsystem
The IWR1443 clock subsystem generates 76 to 81 GHz from an input reference of 40-MHz crystal or external clock. It has a built-in oscillator circuit followed by a clean-up PLL and a RF synthesizer circuit. The output of the RF synthesizer is then processed by an X4 multiplier to create the required frequency in the 76 to 81 GHz spectrum. The RF synthesizer output is modulated by the timing engine block to create the required waveforms for effective sensor operation.
The clean-up PLL also provides a reference clock for the host processor after system wakeup.
The clock subsystem also has built-in mechanisms for detecting the presence of a crystal and monitoring the quality of the generated clock.
Figure 6-2 describes the clock subsystem.
