ZHCSH27B May 2017 – April 2018 IWR1642
PRODUCTION DATA.
- 1 器件概述
- 2 修订历史记录
- 3 Device Comparison
- 4 Terminal Configuration and Functions
-
5 Specifications
- 5.1 Absolute Maximum Ratings
- 5.2 ESD Ratings
- 5.3 Power-On Hours (POH)
- 5.4 Recommended Operating Conditions
- 5.5 Power Supply Specifications
- 5.6 Power Consumption Summary
- 5.7 RF Specification
- 5.8 CPU Specifications
- 5.9 Thermal Resistance Characteristics for FCBGA Package [ABL0161]
- 5.10
Timing and Switching Characteristics
- 5.10.1 Power Supply Sequencing and Reset Timing
- 5.10.2 Input Clocks and Oscillators
- 5.10.3
Multibuffered / Standard Serial Peripheral Interface (MibSPI)
- 5.10.3.1 Peripheral Description
- 5.10.3.2
MibSPI Transmit and Receive RAM Organization
- Table 5-7 SPI Timing Conditions
- Table 5-8 SPI Master Mode Switching Parameters (CLOCK PHASE = 0, SPICLK = output, SPISIMO = output, and SPISOMI = input)
- Table 5-9 SPI Master Mode Input Timing Requirements (CLOCK PHASE = 0, SPICLK = output, SPISIMO = output, and SPISOMI = input)
- Table 5-10 SPI Master Mode Switching Parameters (CLOCK PHASE = 1, SPICLK = output, SPISIMO = output, and SPISOMI = input)
- Table 5-11 SPI Master Mode Input Requirements (CLOCK PHASE = 1, SPICLK = output, SPISIMO = output, and SPISOMI = input)
- 5.10.3.3 SPI Slave Mode I/O Timings
- 5.10.3.4 Typical Interface Protocol Diagram (Slave Mode)
- 5.10.4 LVDS Interface Configuration
- 5.10.5 General-Purpose Input/Output
- 5.10.6 Controller Area Network Interface (DCAN)
- 5.10.7 Serial Communication Interface (SCI)
- 5.10.8 Inter-Integrated Circuit Interface (I2C)
- 5.10.9 Quad Serial Peripheral Interface (QSPI)
- 5.10.10 ETM Trace Interface
- 5.10.11 Data Modification Module (DMM)
- 5.10.12 JTAG Interface
- 6 Detailed Description
- 7 Monitoring and Diagnostics
- 8 Applications, Implementation, and Layout
- 9 Device and Documentation Support
- 10Mechanical, Packaging, and Orderable Information
5.10.4 LVDS Interface Configuration
The supports four differential LVDS IOs/Lanes. The lane configuration supported is two Data lanes (LVDS_TXP/M), one Bit Clock lane (LVDS_CLKP/M) and one Frame clock lane (LVDS_FRCLKP/M). The LVDS interface supports the following data rates:
- 900 Mbps (450 MHz DDR Clock)
- 600 Mbps (300 MHz DDR Clock)
- 450 Mbps (225 MHz DDR Clock)
- 400 Mbps (200 MHz DDR Clock)
- 300 Mbps (150 MHz DDR Clock)
- 225 Mbps (112.5 MHz DDR Clock)
- 150 Mbps (75 MHz DDR Clock)
Note that the bit clock is in DDR format and hence the numbers of toggles in the clock is equivalent to data.
Figure 5-11 LVDS Interface Lane Configuration And Relative Timings