ZHCST57 May   2023 IWR1843AOP

PRODUCTION DATA  

  1.   1
  2. 特性
  3. 应用
  4. 说明
    1. 3.1 功能方框图
  5. Revision History
  6. Device Comparison
    1. 5.1 Related Products
  7. Terminal Configuration and Functions
    1. 6.1 Pin Diagram
    2. 6.2 Pin Attributes
    3. 6.3 Signal Descriptions
      1. 6.3.1 Pin Functions - Digital and Analog [ALP Package]
  8. Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Power-On Hours (POH)
    4. 7.4  Recommended Operating Conditions
    5. 7.5  Power Supply Specifications
    6. 7.6  Power Consumption Summary
    7. 7.7  RF Specification
    8. 7.8  CPU Specifications
    9. 7.9  Thermal Resistance Characteristics for FCBGA Package [ALP0180A]
    10. 7.10 Timing and Switching Characteristics
      1. 7.10.1  Antenna Radiation Patterns
        1. 7.10.1.1 Antenna Radiation Patterns for Receiver
        2. 7.10.1.2 Antenna Radiation Patterns for Transmitter
      2. 7.10.2  Antenna Positions
      3. 7.10.3  Power Supply Sequencing and Reset Timing
      4. 7.10.4  Input Clocks and Oscillators
        1. 7.10.4.1 Clock Specifications
      5. 7.10.5  Multibuffered / Standard Serial Peripheral Interface (MibSPI)
        1. 7.10.5.1 Peripheral Description
        2. 7.10.5.2 MibSPI Transmit and Receive RAM Organization
          1. 7.10.5.2.1 SPI Timing Conditions
          2. 7.10.5.2.2 SPI Controller Mode Switching Parameters (CLOCK PHASE = 0, SPICLK = output, SPISIMO = output, and SPISOMI = input)
          3. 7.10.5.2.3 SPI Controller Mode Switching Parameters (CLOCK PHASE = 1, SPICLK = output, SPISIMO = output, and SPISOMI = input)
        3. 7.10.5.3 SPI Peripheral Mode I/O Timings
          1. 7.10.5.3.1 SPI Peripheral Mode Switching Parameters (SPICLK = input, SPISIMO = input, and SPISOMI = output)
        4. 7.10.5.4 Typical Interface Protocol Diagram (Peripheral Mode)
      6. 7.10.6  LVDS Interface Configuration
        1. 7.10.6.1 LVDS Interface Timings
      7. 7.10.7  General-Purpose Input/Output
        1. 7.10.7.1 Switching Characteristics for Output Timing versus Load Capacitance (CL) #GUID-A9917993-C388-4AAC-B9C6-6B2BF583E88E/T4362547-45 #GUID-A9917993-C388-4AAC-B9C6-6B2BF583E88E/T4362547-50
      8. 7.10.8  Controller Area Network Interface (DCAN)
        1. 7.10.8.1 Dynamic Characteristics for the DCANx TX and RX Pins
      9. 7.10.9  Controller Area Network - Flexible Data-rate (CAN-FD)
        1. 7.10.9.1 Dynamic Characteristics for the CANx TX and RX Pins
      10. 7.10.10 Serial Communication Interface (SCI)
        1. 7.10.10.1 SCI Timing Requirements
      11. 7.10.11 Inter-Integrated Circuit Interface (I2C)
        1. 7.10.11.1 I2C Timing Requirements #GUID-D26A1D00-D5E4-49AB-AFF7-B0ED1920A8A5/T4362547-185
      12. 7.10.12 Quad Serial Peripheral Interface (QSPI)
        1. 7.10.12.1 QSPI Timing Conditions
        2. 7.10.12.2 Timing Requirements for QSPI Input (Read) Timings #GUID-F4461E81-32E4-4CB7-B562-43AFC94843D1/T4362547-210 #GUID-F4461E81-32E4-4CB7-B562-43AFC94843D1/T4362547-209
        3. 7.10.12.3 QSPI Switching Characteristics
      13. 7.10.13 ETM Trace Interface
        1. 7.10.13.1 ETMTRACE Timing Conditions
        2. 7.10.13.2 ETM TRACE Switching Characteristics
      14. 7.10.14 Data Modification Module (DMM)
        1. 7.10.14.1 DMM Timing Requirements
      15. 7.10.15 JTAG Interface
        1. 7.10.15.1 JTAG Timing Conditions
        2. 7.10.15.2 Timing Requirements for IEEE 1149.1 JTAG
        3. 7.10.15.3 Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG
  9. Detailed Description
    1. 8.1 Overview
    2. 8.2 功能方框图
    3. 8.3 Subsystems
      1. 8.3.1 RF and Analog Subsystem
        1. 8.3.1.1 Clock Subsystem
        2. 8.3.1.2 Transmit Subsystem
        3. 8.3.1.3 Receive Subsystem
      2. 8.3.2 Processor Subsystem
      3. 8.3.3 Host Interface
      4. 8.3.4 Main Subsystem Cortex-R4F Memory Map
      5. 8.3.5 DSP Subsystem Memory Map
    4. 8.4 Other Subsystems
      1. 8.4.1 ADC Channels (Service) for User Application
        1. 8.4.1.1 GP-ADC Parameter
  10. Monitoring and Diagnostics
    1. 9.1 Monitoring and Diagnostic Mechanisms
      1. 9.1.1 Error Signaling Module
  11. 10Applications, Implementation, and Layout
    1. 10.1 Application Information
    2. 10.2 Reference Schematic
  12. 11Device and Documentation Support
    1. 11.1 Device Nomenclature
    2. 11.2 Tools and Software
    3. 11.3 Documentation Support
    4. 11.4 支持资源
    5. 11.5 Trademarks
    6. 11.6 静电放电警告
    7. 11.7 术语表
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Packaging Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

说明

IWR1843AOP 器件是一款能够在 76GHz 至 81GHz 频带中运行且基于 FMCW 雷达技术的集成式单芯片毫米波传感器,具有高达 4GHz 的连续线性调频脉冲。该器件采用米6体育平台手机版_好二三四 (TI) 的低功耗 45nm RFCMOS 工艺制造,能采用超小型封装实现出色的集成度。IWR1843AOP 是适用于工业应用(如楼宇自动化、工厂自动化、无人机、物料处理、交通监控和监视)中的低功耗、自监控、超精确雷达系统的理想解决方案。

IWR1843AOP 器件是一种自包含单芯片解决方案,能够简化 76GHz 至 81GHz 频带中的毫米波传感器实施。IWR1843AOP 包含一个具有内置 PLL 和 ADC 转换器的单片实施 3TX、4RX 系统。IWR1843AOP 还集成了 DSP 子系统,该子系统包含 TI 用于雷达信号处理的高性能 C674x DSP。该器件包含一个基于 ARM R4F 的处理器子系统,该子系统负责前端配置、控制和校准。简单编程模型更改可支持各种传感器实施,并且能够进行动态重新配置,从而实现多模式传感器。硬件加速器区块 (HWA) 可执行雷达处理,并且有助于以更高级的算法在 DSP 上节省 MIPS。此外,该器件作为完整的平台解决方案进行提供,其中包括 TI 参考设计、软件驱动程序、示例配置、API 指南、培训以及用户文档。

器件信息
器件型号 封装(1) 封装尺寸 托盘/卷带包装
IWR1843ARBGALP FCBGA (180) 15mm × 15mm 托盘
IWR1843ARBGALPR FCBGA (180) 15mm × 15mm 卷带包装
IWR1843ARQGALP FCBGA (180) 15mm × 15mm 托盘
IWR1843ARQGALPR FCBGA (180) 15mm × 15mm 卷带包装
IWR1843ARBSALP FCBGA (180) 15mm × 15mm 安全可靠的器件托盘
IWR1843ARBSALPR FCBGA (180) 15mm × 15mm 安全可靠的器件卷带
更多信息请参阅 节 12机械封装和可订购米6体育平台手机版_好二三四信息