ZHCST57 May 2023 IWR1843AOP
PRODUCTION DATA
- 1
- 1 特性
- 2 应用
- 3 说明
- 4 Revision History
- 5 Device Comparison
- 6 Terminal Configuration and Functions
-
7 Specifications
- 7.1 Absolute Maximum Ratings
- 7.2 ESD Ratings
- 7.3 Power-On Hours (POH)
- 7.4 Recommended Operating Conditions
- 7.5 Power Supply Specifications
- 7.6 Power Consumption Summary
- 7.7 RF Specification
- 7.8 CPU Specifications
- 7.9 Thermal Resistance Characteristics for FCBGA Package [ALP0180A]
- 7.10
Timing and Switching Characteristics
- 7.10.1 Antenna Radiation Patterns
- 7.10.2 Antenna Positions
- 7.10.3 Power Supply Sequencing and Reset Timing
- 7.10.4 Input Clocks and Oscillators
- 7.10.5 Multibuffered / Standard Serial Peripheral Interface (MibSPI)
- 7.10.6 LVDS Interface Configuration
- 7.10.7 General-Purpose Input/Output
- 7.10.8 Controller Area Network Interface (DCAN)
- 7.10.9 Controller Area Network - Flexible Data-rate (CAN-FD)
- 7.10.10 Serial Communication Interface (SCI)
- 7.10.11 Inter-Integrated Circuit Interface (I2C)
- 7.10.12 Quad Serial Peripheral Interface (QSPI)
- 7.10.13 ETM Trace Interface
- 7.10.14 Data Modification Module (DMM)
- 7.10.15 JTAG Interface
- 8 Detailed Description
- 9 Monitoring and Diagnostics
- 10Applications, Implementation, and Layout
- 11Device and Documentation Support
- 12Mechanical, Packaging, and Orderable Information
7.10.6 LVDS Interface Configuration
The supported IWR1843AOP LVDS lane configuration is two Data lanes (LVDS_TXP/M), one Bit Clock lane (LVDS_CLKP/M) and one Frame clock lane (LVDS_FRCLKP/M). The LVDS interface is used for debugging. The LVDS interface supports the following data rates:
- 900 Mbps (450 MHz DDR Clock)
- 600 Mbps (300 MHz DDR Clock)
- 450 Mbps (225 MHz DDR Clock)
- 400 Mbps (200 MHz DDR Clock)
- 300 Mbps (150 MHz DDR Clock)
- 225 Mbps (112.5 MHz DDR Clock)
- 150 Mbps (75 MHz DDR Clock)
Note that the bit clock is in DDR format and hence the numbers of toggles in the clock is equivalent to data.
Figure 7-15 LVDS Interface Lane Configuration And Relative Timings