ZHCSIZ5E October   2018  – June 2021 IWR6443 , IWR6843

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 功能方框图
  5. 5 Revision History
  6. 6 Device Comparison
    1. 6.1 Related Products
  7. 7 Terminal Configuration and Functions
    1. 7.1 Pin Diagram
    2. 7.2 Signal Descriptions
      1. 7.2.1 Signal Descriptions - Digital
      2. 7.2.2 Signal Descriptions - Analog
    3. 7.3 Pin Attributes
  8. 8 Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Power-On Hours (POH)
    4. 8.4  Recommended Operating Conditions
    5. 8.5  Power Supply Specifications
    6. 8.6  Power Consumption Summary
    7. 8.7  RF Specification
    8. 8.8  CPU Specifications
    9. 8.9  Thermal Resistance Characteristics for FCBGA Package [ABL0161]
    10. 8.10 Timing and Switching Characteristics
      1. 8.10.1  Power Supply Sequencing and Reset Timing
      2. 8.10.2  Input Clocks and Oscillators
        1. 8.10.2.1 Clock Specifications
      3. 8.10.3  Multibuffered / Standard Serial Peripheral Interface (MibSPI)
        1. 8.10.3.1 Peripheral Description
        2. 8.10.3.2 MibSPI Transmit and Receive RAM Organization
          1. 8.10.3.2.1 SPI Timing Conditions
          2. 8.10.3.2.2 SPI Master Mode Switching Parameters (CLOCK PHASE = 0, SPICLK = output, SPISIMO = output, and SPISOMI = input) (1) (1) (1)
          3. 8.10.3.2.3 SPI Master Mode Switching Parameters (CLOCK PHASE = 1, SPICLK = output, SPISIMO = output, and SPISOMI = input) (1) (1) (1)
        3. 8.10.3.3 SPI Slave Mode I/O Timings
          1. 8.10.3.3.1 SPI Slave Mode Switching Parameters (SPICLK = input, SPISIMO = input, and SPISOMI = output) (1) (1) (1)
        4. 8.10.3.4 Typical Interface Protocol Diagram (Slave Mode)
      4. 8.10.4  LVDS Interface Configuration
        1. 8.10.4.1 LVDS Interface Timings
      5. 8.10.5  General-Purpose Input/Output
        1. 8.10.5.1 Switching Characteristics for Output Timing versus Load Capacitance (CL) (1) (1)
      6. 8.10.6  Controller Area Network - Flexible Data-rate (CAN-FD)
        1. 8.10.6.1 Dynamic Characteristics for the CANx TX and RX Pins
      7. 8.10.7  Serial Communication Interface (SCI)
        1. 8.10.7.1 SCI Timing Requirements
      8. 8.10.8  Inter-Integrated Circuit Interface (I2C)
        1. 8.10.8.1 I2C Timing Requirements (1)
      9. 8.10.9  Quad Serial Peripheral Interface (QSPI)
        1. 8.10.9.1 QSPI Timing Conditions
        2. 8.10.9.2 Timing Requirements for QSPI Input (Read) Timings (1) (1)
        3. 8.10.9.3 QSPI Switching Characteristics
      10. 8.10.10 ETM Trace Interface
        1. 8.10.10.1 ETMTRACE Timing Conditions
        2. 8.10.10.2 ETM TRACE Switching Characteristics
      11. 8.10.11 Data Modification Module (DMM)
        1. 8.10.11.1 DMM Timing Requirements
      12. 8.10.12 JTAG Interface
        1. 8.10.12.1 JTAG Timing Conditions
        2. 8.10.12.2 Timing Requirements for IEEE 1149.1 JTAG
        3. 8.10.12.3 Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Subsystems
      1. 9.3.1 RF and Analog Subsystem
        1. 9.3.1.1 Clock Subsystem
        2. 9.3.1.2 Transmit Subsystem
        3. 9.3.1.3 Receive Subsystem
      2. 9.3.2 Processor Subsystem
      3. 9.3.3 Host Interface
      4. 9.3.4 Main Subsystem Cortex-R4F
      5. 9.3.5 DSP Subsystem
      6. 9.3.6 Hardware Accelerator
    4. 9.4 Other Subsystems
      1. 9.4.1 ADC Channels (Service) for User Application
        1. 9.4.1.1 GP-ADC Parameter
  10. 10Monitoring and Diagnostics
    1. 10.1 Monitoring and Diagnostic Mechanisms
      1. 10.1.1 Error Signaling Module
  11. 11Applications, Implementation, and Layout
    1. 11.1 Application Information
    2. 11.2 Reference Schematic
  12. 12Device and Documentation Support
    1. 12.1 Device Nomenclature
    2. 12.2 Tools and Software
    3. 12.3 Documentation Support
    4. 12.4 支持资源
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 术语表
  13. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Packaging Information
    2. 13.2 Tray Information for ABL, 10.4 × 10.4 mm

封装选项

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)
  • ABL|161
散热焊盘机械数据 (封装 | 引脚)
订购信息

7.3 Pin Attributes

Table 7-1 Pin Attributes (ABL0161 Package)
BALL NUMBER [1] BALL NAME [2] SIGNAL NAME [3] PINCNTL ADDRESS[4] MODE [5][9] TYPE [6] BALL RESET STATE [7] PULL UP/DOWN TYPE [8]
H13 GPIO_0 GPIO_13 0xFFFFEA04 0 IO Output Disabled Pull Down
GPIO_0 1 IO
PMIC_CLKOUT 2 O
EPWM1B 10 O
ePWM2A 11 O
J13 GPIO_1 GPIO_16 0xFFFFEA08 0 IO Output Disabled Pull Down
GPIO_1 1 IO
SYNC_OUT 2 O
DMM_MUX_IN 12 I
SPIB_CS_N_1 13 IO
SPIB_CS_N_2 14 IO
EPWM1SYNCI 15 I
K13 GPIO_2 GPIO_26 0xFFFFEA64 0 IO Output Disabled Pull Down
GPIO_2 1 IO
OSC_CLKOUT 2 O
MSS_UARTB_TX 7 O
BSS_UART_TX 8 O
SYNC_OUT 9 O
PMIC_CLKOUT 10 O
CHIRP_START 11 O
CHIRP_END 12 O
FRAME_START 13 O
R4 GPIO_31 TRACE_DATA_0 0xFFFFEA7C 0 O Output Disabled Pull Down
GPIO_31 1 IO
DMM0 2 I
MSS_UARTA_TX 4 IO
P5 GPIO_32 TRACE_DATA_1 0xFFFFEA80 0 O Output Disabled Pull Down
GPIO_32 1 IO
DMM1 2 I
R5 GPIO_33 TRACE_DATA_2 0xFFFFEA84 0 O Output Disabled Pull Down
GPIO_33 1 IO
DMM2 2 I
P6 GPIO_34 TRACE_DATA_3 0xFFFFEA88 0 O Output Disabled Pull Down
GPIO_34 1 IO
DMM3 2 I
EPWM3SYNCO 4 O
R7 GPIO_35 TRACE_DATA_4 0xFFFFEA8C 0 O Output Disabled Pull Down
GPIO_35 1 IO
DMM4 2 I
EPWM2SYNCO 4 O
P7 GPIO_36 TRACE_DATA_5 0xFFFFEA90 0 O Output Disabled Pull Down
GPIO_36 1 IO
DMM5 2 I
MSS_UARTB_TX 5 O
R8 GPIO_37 TRACE_DATA_6 0xFFFFEA94 0 O Output Disabled Pull Down
GPIO_37 1 IO
DMM6 2 I
BSS_UART_TX 5 O
P8 GPIO_38 TRACE_DATA_7 0xFFFFEA98 0 O Output Disabled Pull Down
GPIO_38 1 IO
DMM7 2 I
DSS_UART_TX 5 O
N15 GPIO_47 TRACE_CLK 0xFFFFEABC 0 O Output Disabled Pull Down
GPIO_47 1 IO
DMM_CLK 2 I
N14 DMM_SYNC TRACE_CTL 0xFFFFEAC0 0 O Output Disabled Pull Down
DMM_SYNC 2 I
N8 MCU_CLKOUT GPIO_25 0xFFFFEA60 0 IO Output Disabled Pull Down
MCU_CLKOUT 1 O
CHIRP_START 2 O
CHIRP_END 6 O
FRAME_START 7 O
EPWM1A 12 O
N7 NERROR_IN NERROR_IN 0xFFFFEA44 0 I Input
N6 NERROR_OUT NERROR_OUT 0xFFFFEA4C 0 O Hi-Z (Open Drain)
P9 PMIC_CLKOUT SOP[2] 0xFFFFEA68 During Power Up I Output Disabled Pull Down
GPIO_27 0 IO
PMIC_CLKOUT 1 O
CHIRP_START 6 O
CHIRP_END 7 O
FRAME_START 8 O
EPWM1B 11 O
EPWM2A 12 O
R13 QSPI[0] GPIO_8 0xFFFFEA2C 0 IO Output Disabled Pull Down
QSPI[0] 1 IO
SPIB_MISO 2 IO
N12 QSPI[1] GPIO_9 0xFFFFEA30 0 IO Output Disabled Pull Down
QSPI[1] 1 I
SPIB_MOSI 2 IO
SPIB_CS_N_2 8 IO
R14 QSPI[2] GPIO_10 0xFFFFEA34 0 IO Output Disabled Pull Down
QSPI[2] 1 I
CAN_FD_TX 8 O
P12 QSPI[3] GPIO_11 0xFFFFEA38 0 IO Output Disabled Pull Down
QSPI[3] 1 I
CAN_FD_RX 8 I
R12 QSPI_CLK GPIO_7 0xFFFFEA3C 0 IO Output Disabled Pull Down
QSPI_CLK 1 O
SPIB_CLK 2 IO
DSS_UART_TX 6 O
P11 QSPI_CS_N GPIO_6 0xFFFFEA40 0 IO Output Disabled Pull Up
QSPI_CS_N 1 O
SPIB_CS_N 2 IO
N4 RS232_RX GPIO_15 0xFFFFEA74 0 IO Input Enabled Pull Up
RS232_RX 1 I
MSS_UARTA_RX 2 I
BSS_UART_TX 6 IO
MSS_UARTB_RX 7 IO
CAN_FD_RX 8 I
I2C_SCL 9 IO
EPWM2A 10 O
EPWM2B 11 O
EPWM3A 12 O
N5 RS232_TX GPIO_14 0xFFFFEA78 0 IO Output Enabled
RS232_TX 1 O
MSS_UARTA_TX 5 IO
MSS_UARTB_TX 6 IO
BSS_UART_TX 7 IO
CAN_FD_TX 10 O
I2C_SDA 11 IO
EPWM1A 12 O
EPWM1B 13 O
NDMM_EN 14 I
EPWM2A 15 O
E13 SPIA_CLK GPIO_3 0xFFFFEA14 0 IO Output Disabled Pull Up
SPIA_CLK 1 IO
DSS_UART_TX 7 O
E15 SPIA_CS_N GPIO_30 0xFFFFEA18 0 IO Output Disabled Pull Up
SPIA_CS_N 1 IO
E14 SPIA_MISO GPIO_20 0xFFFFEA10 0 IO Output Disabled Pull Up
SPIA_MISO 1 IO
CAN_FD_TX 2 O
D13 SPIA_MOSI GPIO_19 0xFFFFEA0C 0 IO Output Disabled Pull Up
SPIA_MOSI 1 IO
CAN_FD_RX 2 I
DSS_UART_TX 8 O
F14 SPIB_CLK GPIO_5 0xFFFFEA24 0 IO Output Disabled Pull Up
SPIB_CLK 1 IO
MSS_UARTA_RX 2 I
MSS_UARTB_TX 6 O
BSS_UART_TX 7 O
CAN_FD_RX 8 I
H14 SPIB_CS_N GPIO_4 0xFFFFEA28 0 IO Output Disabled Pull Up
SPIB_CS_N 1 IO
MSS_UARTA_TX 2 O
MSS_UARTB_TX 6 O
BSS_UART_TX 7 IO
QSPI_CLK_EXT 8 I
CAN_FD_TX 9 O
G14 SPIB_MISO GPIO_22 0xFFFFEA20 0 IO Output Disabled Pull Up
SPIB_MISO 1 IO
I2C_SCL 2 IO
DSS_UART_TX 6 O
F13 SPIB_MOSI GPIO_21 0xFFFFEA1C 0 IO Output Disabled Pull Up
SPIB_MOSI 1 IO
I2C_SDA 2 IO
P13 SPI_HOST_INTR GPIO_12 0xFFFFEA00 0 IO Output Disabled Pull Down
SPI_HOST_INTR 1 O
SPIB_CS_N_1 6 IO
P4 SYNC_IN GPIO_28 0xFFFFEA6C 0 IO Output Disabled Pull Down
SYNC_IN 1 I
MSS_UARTB_RX 6 IO
DMM_MUX_IN 7 I
SYNC_OUT 9 O
G13 SYNC_OUT SOP[1] 0xFFFFEA70 During Power Up I Output Disabled Pull Down
GPIO_29 0 IO
SYNC_OUT 1 O
DMM_MUX_IN 9 I
SPIB_CS_N_1 10 IO
SPIB_CS_N_2 11 IO
P10 TCK GPIO_17 0xFFFFEA50 0 IO Input Enabled Pull Down
TCK 1 I
MSS_UARTB_TX 2 O
CAN_FD_TX 8 O
R11 TDI GPIO_23 0xFFFFEA58 0 IO Input Enabled Pull Up
TDI 1 I
MSS_UARTA_RX 2 I
N13 TDO SOP[0] 0xFFFFEA5C During Power Up I Output Enabled
GPIO_24 0 IO
TDO 1 O
MSS_UARTA_TX 2 O
MSS_UARTB_TX 6 O
BSS_UART_TX 7 O
NDMM_EN 9 I
N10 TMS GPIO_18 0xFFFFEA54 0 IO Input Enabled Pull Down
TMS 1 I
BSS_UART_TX 2 O
CAN_FD_RX 6 I
N9 WARM_RESET WARM_RESET 0xFFFFEA48 0 IO Hi-Z Input (Open Drain)

The following list describes the table column headers:

  1. BALL NUMBER: Ball numbers on the bottom side associated with each signal on the bottom.
  2. BALL NAME: Mechanical name from package device (name is taken from muxmode 0).
  3. SIGNAL NAME: Names of signals multiplexed on each ball (also notice that the name of the ball is the signal name in muxmode 0).
  4. PINCNTL ADDRESS: MSS Address for PinMux Control
  5. MODE: Multiplexing mode number: value written to PinMux Cntl register to select specific Signal name for this Ball number. Mode column has bit range value.
  6. TYPE: Signal type and direction:
    • I = Input
    • O = Output
    • IO = Input or Output
  7. BALL RESET STATE: The state of the terminal at power-on reset
  8. PULL UP/DOWN TYPE: indicates the presence of an internal pullup or pulldown resistor. Pullup and pulldown resistors can be enabled or disabled via software.
    • Pull Up: Internal pullup
    • Pull Down: Internal pulldown
    • An empty box means No pull.
  9. Pin Mux Control Value maps to lower 4 bits of register.

IO MUX registers are available in the MSS memory map and the respective mapping to device pins is as follows:

Table 7-2 PAD IO Control Registers
Default Pin/Ball Name Package Ball /Pin (Address) Pin Mux Config Register
SPI_HOST_INTR P13 0xFFFFEA00
GPIO_0 H13 0xFFFFEA04
GPIO_1 J13 0xFFFFEA08
SPIA_MOSI D13 0xFFFFEA0C
SPIA_MISO E14 0xFFFFEA10
SPIA_CLK E13 0xFFFFEA14
SPIA_CS_N E15 0xFFFFEA18
SPIB_MOSI F13 0xFFFFEA1C
SPIB_MISO G14 0xFFFFEA20
SPIB_CLK F14 0xFFFFEA24
SPIB_CS_N H14 0xFFFFEA28
QSPI[0] R13 0xFFFFEA2C
QSPI[1] N12 0xFFFFEA30
QSPI[2] R14 0xFFFFEA34
QSPI[3] P12 0xFFFFEA38
QSPI_CLK R12 0xFFFFEA3C
QSPI_CS_N P11 0xFFFFEA40
NERROR_IN N7 0xFFFFEA44
WARM_RESET N9 0xFFFFEA48
NERROR_OUT N6 0xFFFFEA4C
TCK P10 0xFFFFEA50
TMS N10 0xFFFFEA54
TDI R11 0xFFFFEA58
TDO N13 0xFFFFEA5C
MCU_CLKOUT N8 0xFFFFEA60
GPIO_2 K13 0xFFFFEA64
PMIC_CLKOUT P9 0xFFFFEA68
SYNC_IN P4 0xFFFFEA6C
SYNC_OUT G13 0xFFFFEA70
RS232_RX N4 0xFFFFEA74
RS232_TX N5 0xFFFFEA78
GPIO_31 R4 0xFFFFEA7C
GPIO_32 P5 0xFFFFEA80
GPIO_33 R5 0xFFFFEA84
GPIO_34 P6 0xFFFFEA88
GPIO_35 R7 0xFFFFEA8C
GPIO_36 P7 0xFFFFEA90
GPIO_37 R8 0xFFFFEA94
GPIO_38 P8 0xFFFFEA98
GPIO_47 N15 0xFFFFEABC
DMM_SYNC N14 0xFFFFEAC0

The register layout is as follows:

Table 7-3 PAD IO Register Bit Descriptions
BIT FIELD TYPE RESET (POWER ON DEFAULT) DESCRIPTION
31-11 NU RW 0 Reserved
10 SC RW 0 IO slew rate control:
0 = Higher slew rate
1 = Lower slew rate
9 PUPDSEL RW 0 Pullup/PullDown Selection
0 = Pull Down
1 = Pull Up (This field is valid only if Pull Inhibit is set as '0')
8 PI RW 0 Pull Inhibit/Pull Disable
0 = Enable
1 = Disable
7 OE_OVERRIDE RW 1 Output Override
6 OE_OVERRIDE_CTRL RW 1 Output Override Control:
(A '1' here overrides any o/p manipulation of this IO by any of the peripheral block hardware it is associated with for example a SPI Chip select)
5 IE_OVERRIDE RW 0 Input Override
4 IE_OVERRIDE_CTRL RW 0 Input Override Control:
(A '1' here overrides any i/p value on this IO with a desired value)
3-0 FUNC_SEL RW 1 Function select for Pin Multiplexing (Refer to the Pin Mux Sheet)
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