米6体育平台手机版

ZHCSLB7B April 2020 – July 2022 IWR6843AOP

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ALP|180

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8.10.5.2.2 SPI Controller Mode Switching Parameters (CLOCK PHASE = 0, SPICLK = output,
SPISIMO = output, and SPISOMI = input)⁽¹⁾⁽²⁾⁽³⁾

NO.	PARAMETER			MIN	MAX	UNIT
1	t_c(SPC)M	Cycle time, SPICLK⁽⁴⁾		25	256_tc(VCLK)	ns
2⁽⁴⁾	t_w(SPCH)M	Pulse duration, SPICLK high (clock polarity = 0)		0.5t_c(SPC)M – 4	0.5t_c(SPC)M + 4	ns
2⁽⁴⁾	t_w(SPCL)M	Pulse duration, SPICLK low (clock polarity = 1)		0.5t_c(SPC)M – 4	0.5t_c(SPC)M + 4	ns
3⁽⁴⁾	t_w(SPCL)M	Pulse duration, SPICLK low (clock polarity = 0)		0.5t_c(SPC)M – 4	0.5t_c(SPC)M + 4	ns
3⁽⁴⁾	t_w(SPCH)M	Pulse duration, SPICLK high (clock polarity = 1)		0.5t_c(SPC)M – 4	0.5t_c(SPC)M + 4	ns
4⁽⁴⁾	t_{d(SPCH-SIMO)M}	Delay time, SPISIMO valid before SPICLK low, (clock polarity = 0)		0.5t_c(SPC)M – 3		ns
4⁽⁴⁾	t_{d(SPCL-SIMO)M}	Delay time, SPISIMO valid before SPICLK high, (clock polarity = 1)		0.5t_c(SPC)M – 3		ns
5⁽⁴⁾	t_{v(SPCL-SIMO)M}	Valid time, SPISIMO data valid after SPICLK low, (clock polarity = 0)		0.5t_c(SPC)M – 10.5		ns
5⁽⁴⁾	t_{v(SPCH-SIMO)M}	Valid time, SPISIMO data valid after SPICLK high, (clock polarity = 1)		0.5t_c(SPC)M – 10.5		ns
6⁽⁵⁾	t_C2TDELAY	Setup time CS active until SPICLK high (clock polarity = 0)	CSHOLD = 0	(C2TDELAY+2)*t_c(VCLK) – 7.5	(C2TDELAY+2) * t_c(VCLK) + 7	ns
		Setup time CS active until SPICLK high (clock polarity = 0)	CSHOLD = 1	(C2TDELAY +3) * t_c(VCLK) – 7.5	(C2TDELAY+3) * t_c(VCLK) + 7
		Setup time CS active until SPICLK low (clock polarity = 1)	CSHOLD = 0	(C2TDELAY+2)*t_c(VCLK) – 7.5	(C2TDELAY+2) * t_c(VCLK) + 7
		Setup time CS active until SPICLK low (clock polarity = 1)	CSHOLD = 1	(C2TDELAY +3) * t_c(VCLK) – 7.5	(C2TDELAY+3) * t_c(VCLK) + 7
7⁽⁵⁾	t_T2CDELAY	Hold time, SPICLK low until CS inactive (clock polarity = 0)		0.5t_c(SPC)M + (T2CDELAY + 1) t_c(VCLK) – 7	0.5t_c(SPC)M + (T2CDELAY + 1) t_c(VCLK) + 7.5	ns
7⁽⁵⁾	t_T2CDELAY	Hold time, SPICLK high until CS inactive (clock polarity = 1)		0.5t_c(SPC)M + (T2CDELAY + 1) t_c(VCLK) – 7	0.5t_c(SPC)M + (T2CDELAY + 1) t_c(VCLK) + 7.5	ns
8⁽⁴⁾	t_{su(SOMI-SPCL)M}	Setup time, SPISOMI before SPICLK low (clock polarity = 0)		5		ns
8⁽⁴⁾	t_{su(SOMI-SPCH)M}	Setup time, SPISOMI before SPICLK high (clock polarity = 1)		5		ns
9⁽⁴⁾	t_{h(SPCL-SOMI)M}	Hold time, SPISOMI data valid after SPICLK low (clock polarity = 0)		3		ns
9⁽⁴⁾	t_{h(SPCH-SOMI)M}	Hold time, SPISOMI data valid after SPICLK high (clock polarity = 1)		3		ns

(1) The MASTER bit (SPIGCRx.0) is set and the CLOCK PHASE bit (SPIFMTx.16) is cleared (where x= 0 or 1).

(2) t_{c(MSS_VCLK)} = main subsystem clock time = 1 / f_{(MSS_VCLK)}. For more details, see the Technical Reference Manual.

(3) When the SPI is in Controller mode, the following must be true: For PS values from 1 to 255: t_c(SPC)M ≥ (PS +1)t_{c(MSS_VCLK)} ≥ 25ns, where PS is the prescale value set in the SPIFMTx.[15:8] register bits. For PS values of 0: t_c(SPC)M = 2t_{c(MSS_VCLK)} ≥ 25ns.

(4) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPIFMTx.17).

(5) C2TDELAY and T2CDELAY is programmed in the SPIDELAY register

Figure 8-6 SPI Controller Mode External Timing (CLOCK PHASE = 0)

Figure 8-7 SPI Controller Mode Chip Select Timing (CLOCK PHASE = 0)

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8.10.5.2.2 SPI Controller Mode Switching Parameters (CLOCK PHASE = 0, SPICLK = output, SPISIMO = output, and SPISOMI = input)(1)(2)(3)

8.10.5.2.2 SPI Controller Mode Switching Parameters (CLOCK PHASE = 0, SPICLK = output,
SPISIMO = output, and SPISOMI = input)⁽¹⁾⁽²⁾⁽³⁾