7.5.1 SPI Description

A typical serial interface transaction begins with an 8-bit instruction, which is comprised of a read/write bit (MSB, R=1) and a 7-bit address of the register, followed by a Data field which is typically 8 bits. However, the data field can be extended to a multiple of 8 bits by providing sufficient SPI clocks. Refer to the Extended SPI Transactions section for more information.

Figure 15. Serial Interface Protocol

Each assertion of chip select bar (CSB) starts a new register access. The R/Wb bit in the command field configures the type of the access. A value of 0 indicates a write operation, and a value of 1 indicates a read operation. All output data is driven on the falling edge of the serial clock (SCLK), and all input data is sampled on the rising edge of the serial clock (SCLK). Data is written into the register on the rising edge of the 16th clock. It is required to deassert CSB after the 16th clock. Remember that if CSB is deasserted before the 16th clock, no data write will occur.

The LDC1001 utilizes a 4-wire SPI interface to access control and data registers. The LDC1001 is an SPI slave device and does not initiate any transactions.