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ZHCSF01 April 2016 LDC1312-Q1 , LDC1314-Q1

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8 Detailed Description

8.1 Overview

Conductive objects brought in contact with an AC electromagnetic (EM) field will induce field changes that can be detected using a sensor such as an inductor. Conveniently, an inductor, along with a capacitor, can be used to construct an L-C resonator, also known as an L-C tank, which can be used to produce an EM field. In the case of an L-C tank, the effect of the field disturbance is an apparent shift in the inductance of the sensor, which can be observed as a shift in the resonant frequency. Using this principle, the LDC1312/1314 is an inductance-to-digital converter (LDC) that measures the oscillation frequency of an LC resonator. The device outputs a digital value that is proportional to frequency. This frequency measurement can be converted to an equivalent inductance.

8.2 Functional Block Diagram

LDC1312-Q1 LDC1314-Q1 bd_LDC1x12_LDC1x14_snoscy9.gif

Figure 10. Block Diagrams for the LDC1312 (Left) and LDC1314 (Right)

The LDC1312/LDC1314 is composed of front-end resonant circuit drivers, followed by a multiplexer that sequences through the active channels, connecting them to the core that measures and digitizes the sensor frequency (f_SENSOR). The core uses a reference frequency (f_REF) to measure the sensor frequency. f_REF is derived from either an internal reference clock (oscillator), or an externally supplied clock. The digitized output for each channel is proportional to the ratio of f_SENSOR/f_REF. The I2C interface is used to support device configuration and to transmit the digitized frequency values to a host processor. The LDC can be placed in shutdown mode, saving current, using the SD pin. The INTB pin may be configured to notify the host of changes in system status.

8.3 Feature Description

8.3.1 Clocking Architecture

Figure 11 shows the clock dividers and multiplexers of the LDC.

LDC1312-Q1 LDC1314-Q1 clk_diag_LDC161x_snoscy9.gif

Figure 11. Clocking Diagram

(1) LDC1314 only

In Figure 11, the key clocks are f_IN, f_REF, and f_CLK. f_CLK is selected from either the internal clock source or external clock source (CLKIN). The frequency measurement reference clock, f_REF, is derived from the f_CLK source. TI recommends that precision applications use an external master clock that offers the stability and accuracy requirements needed for the application. The internal oscillator may be used in applications that require low cost and do not require high precision. The f_INx clock is derived from sensor frequency for a channel x, f_SENSORx. f_REFx and f_INx must meet the requirements listed in Table 1, depending on whether f_CLK (master clock) is the internal or external clock.

Table 1. Clock Configuration Requirements

MODE⁽¹⁾	CLKIN SOURCE	VALID f_REFx RANGE (MHz)	VALID f_INx RANGE	SET CHx_FIN_DIVIDER to	SET CHx_SETTLECOUNT to	SET CHx_RCOUNT to
Multi-Channel	Internal	f_REFx < 55	< f_REFx /4	≥ b0001 ⁽²⁾	> 3	> 8
Multi-Channel	External	f_REFx < 40
Single-Channel	Either external or internal	f_REFx < 35

(1) Channels 2 and 3 are only available for LDC1314

(2) If f_SENSOR ≥ 8.75 MHz, then CHx_FIN_DIVIDER must be ≥ 2

Table 2 shows the clock configuration registers for all channels.

Table 2. Clock Configuration Registers

CHANNEL⁽¹⁾	CLOCK	REGISTER	FIELD [ BIT(S) ]	VALUE
All	f_CLK = Master Clock Source	CONFIG, addr 0x1A	REF_CLK_SRC [9]	b0 = internal oscillator is used as the master clock b1 = external clock source is used as the master clock
0	f_REF0	CLOCK_DIVIDERS_CH0, addr 0x14	CH0_FREF_DIVIDER [9:0]	f_REF0 = f_CLK / CH0_FREF_DIVIDER
1	f_REF1	CLOCK_DIVIDERS_CH1, addr 0x15	CH1_FREF_DIVIDER [9:0]	f_REF1 = f_CLK / CH1_FREF_DIVIDER
2	f_REF2	CLOCK_DIVIDERS_CH2, addr 0x16	CH2_FREF_DIVIDER [9:0]	f_REF2 = f_CLK / CH2_FREF_DIVIDER
3	f_REF3	CLOCK_DIVIDERS_CH3, addr 0x17	CH3_FREF_DIVIDER [9:0]	f_REF3 = f_CLK / CH3_FREF_DIVIDER
0	f_IN0	CLOCK_DIVIDERS_CH0, addr 0x14	CH0_FIN_DIVIDER [15:12]	f_IN0 = f_SENSOR0 / CH0_FIN_DIVIDER
1	f_IN1	CLOCK_DIVIDERS_CH1, addr 0x15	CH1_FIN_DIVIDER [15:12]	f_IN1 = f_SENSOR1 / CH1_FIN_DIVIDER
2	f_IN2	CLOCK_DIVIDERS_CH2, addr 0x16	CH2_FIN_DIVIDER [15:12]	f_IN2 = f_SENSOR2/ CH2_FIN_DIVIDER
3	f_IN3	CLOCK_DIVIDERS_CH3, addr 0x17	CH3_FIN_DIVIDER [15:12]	f_IN3 = f_SENSOR3 / CH3_FIN_DIVIDER

(1) Channels 2 and 3 are only available for LDC1314

8.3.2 Multi-Channel and Single Channel Operation

The multi-channel package of the LDC enables the user to save board space and support flexible system design. For example, temperature drift can often cause a shift in component values, resulting in a shift in resonant frequency of the sensor. Using a 2nd sensor as a reference provides the capability to cancel out a temperature shift. When operated in multi-channel mode, the LDC sequentially samples the active channels. In single channel mode, the LDC samples a single channel, which is selectable. Table 3 shows the registers and values that are used to configure either multi-channel or single channel modes.

Table 3. Single and Multi-Channel Configuration Registers

MODE	REGISTER	FIELD [ BIT(S) ]	VALUE⁽¹⁾
Single channel	CONFIG, addr 0x1A	ACTIVE_CHAN [15:14]	00 = chan 0
			01 = chan 1
			10 = chan 2
			11 = chan 3
	MUX_CONFIG addr 0x1B	AUTOSCAN_EN [15]	0 = continuous conversion on a single channel (default)
Multi-channel	MUX_CONFIG addr 0x1B	AUTOSCAN_EN [15]	1 = continuous conversion on multiple channels
	MUX_CONFIG addr 0x1B	RR_SEQUENCE [14:13]	00 = Ch0, Ch 1
			01 = Ch0, Ch 1, Ch 2
			10 = Ch0, CH1, Ch2, Ch3

(1) Channels 2 and 3 are only available for LDC1314

The digitized sensor measurement for each channel (DATAx) represents the ratio of the sensor frequency to the reference frequency. The data outputs represent the 12 MSBs of a 16-bit result:

Equation 1. DATAx/ 2¹² = f_SENSORx/f_REFx

The sensor frequency can be calculated from:

Equation 2. LDC1312-Q1 LDC1314-Q1 eq16_snoscy9.gif

Table 4 shows the registers that contain the fixed point sample values for each channel.

Table 4. LDC1314/1312 Sample Data Registers

CHANNEL⁽¹⁾	REGISTER	FIELD NAME [BITS(S) ]	VALUE
0	DATA_MSB_CH0, addr 0x00	DATA0 [11:0]	12 bits of the 16 bit result. 0x000 = under range 0xfff = over range
1	DATA_MSB_CH1, addr 0x02	DATA1 [11:0]	12 bits of the 16 bit result. 0x000 = under range 0xfff = over range
2	DATA_MSB_CH2, addr 0x04	DATA2 [11:0]	12 bits of the 16 bit result. 0x000 = under range 0xfff = over range
3	DATA_MSB_CH3, addr 0x06	DATA3 [11:0]	12 bits of the 16 bit result. 0x000 = under range 0xfff = over range

(1) Channels 2 and 3 available for LDC1314 only.

When the LDC sequences through the channels in multi-channel mode, the dwell time interval for each channel is the sum of 3 parts: sensor activation time + conversion time + channel switch delay.

The sensor activation time is the amount of settling time required for the sensor oscillation to stabilize, as shown in Figure 12. The settling wait time is programmable and should be set to a value that is long enough to allow stable oscillation. The settling wait time for channel x is given by:

Equation 3. t_Sx = (CHX_SETTLECOUNTˣ16)/f_REFx

Table 5 shows the registers and values for configuring the settling time for each channel.

LDC1312-Q1 LDC1314-Q1 sequential_mode_ch_seq_snoscy9.gif

Figure 12. Multi-channel Mode Sequencing

LDC1312-Q1 LDC1314-Q1 single_ch_conv_mode_snoscy9.gif

Figure 13. Single-channel Mode Sequencing

Table 5. Settling Time Register Configuration

CHANNEL⁽¹⁾	REGISTER	FIELD	CONVERSION TIME⁽²⁾
0	SETTLECOUNT_CH0, addr 0x10	CH0_SETTLECOUNT (15:0)	(CH0_SETTLECOUNT*16)/f_REF0
1	SETTLECOUNT_CH1, addr 0x11	CH1_SETTLECOUNT (15:0)	(CH1_SETTLECOUNT*16)/f_REF1
2	SETTLECOUNT_CH2, addr 0x12	CH2_SETTLECOUNT (15:0)	(CH2_SETTLECOUNT*16)/f_REF2
3	SETTLECOUNT_CH3, addr 0x13	CH3_SETTLECOUNT (15:0)	(CH3_SETTLECOUNT*16)/f_REF3

(1) Channels 2 and 3 are available only in the LDC1314.

(2) f_REFx is the reference frequency configured for the channel.

The SETTLECOUNT for any channel x must satisfy:

Equation 4. CHx_SETTLECOUNT ≥ Q_SENSORx × f_REFx / (16 × f_SENSORx)

where

f_SENSORx = Frequency of the Sensor on Channel x
f_REFx = Reference frequency for Channel x
Q_SENSORx = Quality factor of the sensor on Channel x, where Q can be calculated by:

Equation 5. LDC1312-Q1 LDC1314-Q1 eq02_snoscy9.gif

Round the result to the next highest integer (for example, if Equation 4 recommends a minimum value of 6.08, program the register to 7 or higher).

L, R_P and C values can be obtained by using Texas Instrument’s WEBENCH® for the coil design.

The conversion time represents the number of reference clock cycles used to measure the sensor frequency. It is set by the CHx_RCOUNT register for the channel. The conversion time for any channel x is:

Equation 6. t_Cx = (CHx_RCOUNT ˣ 16 + 4) /f_REFx

The reference count value must be chosen to support the required number of effective bits (ENOB). For details, refer to the application note Optimizing L Measurement Resolution for the LDC161x and LDC1101.

Table 6. Conversion Time Configuration Registers, Channels 0 - 3⁽¹⁾

CHANNEL	REGISTER	FIELD [ BIT(S) ]	CONVERSION TIME
0	RCOUNT_CH0, addr 0x08	CH0_RCOUNT (15:0)	(CH0_RCOUNT*16)/f_REF0
1	RCOUNT_CH1, addr 0x09	CH1_RCOUNT (15:0)	(CH1_RCOUNT*16)/f_REF1
2	RCOUNT_CH2, addr 0x0A	CH2_RCOUNT (15:0)	(CH2_RCOUNT*16)/f_REF2
3	RCOUNT_CH3, addr 0x0B	CH3_RCOUNT (15:0)	(CH3_RCOUNT*16)/f_REF3

(1) Channels 2 and 3 are available only for LDC1314.

The typical channel switch delay time between the end of conversion and the beginning of sensor activation of the subsequent channel is:

Equation 7. Channel Switch Delay = 692 ns + 5 / f_ref

The deterministic conversion time of the LDC allows data polling at a fixed interval. A data ready flag (DRDY) is also available for interrupt driven system designs (see the STATUS register description in Register Maps).

An offset value may be subtracted from each DATA value to compensate for a frequency offset or maximize the dynamic range of the sample data. The offset values should be < f_{SENSORx_MIN} / f_REFx. Otherwise, the offset might be so large that it masks the LSBs which are changing.

Table 7. Frequency Offset Registers

CHANNEL⁽¹⁾	REGISTER	FIELD [ BIT(S) ]	VALUE
0	OFFSET_CH0, addr 0x0C	CH0_OFFSET [ 15:0 ]	f_OFFSET0 = CH0_OFFSET * (f_REF0/2¹⁶)
1	OFFSET_CH1, addr 0x0D	CH1_OFFSET [ 15:0 ]	f_OFFSET1= CH1_OFFSET * (f_REF1/2¹⁶)
2	OFFSET_CH2, addr 0x0E	CH2_OFFSET [ 15:0 ]	f_OFFSET2 = CH2_OFFSET * (f_REF2/2¹⁶)
3	OFFSET_CH3, addr 0x0F	CH3_OFFSET [ 15:0 ]	f_OFFSET3= CH3_OFFSET * (f_REF3/2¹⁶)

(1) Channels 2 and 3 are only available for LDC1314

Internally, the LDC measures with 16bits of resolution, while the conversion output word width is only 12bits. For systems in which the sensor signal variation is less than 25% of the full scale range, the LDC can report conversion results with higher resolution by setting the output gain. The output gain is applied to all device channels. An output gain can be used to apply a 2-bit, 3-bit, or 4-bit shift to the output code for all channels, allowing access to the 4LSBs of the original 16-bit result. The MSBs of the sample are shifted out when a gain is applied. Do not use the output gain if the MSBs of any active channel are toggling, as the MSBs for that channel will be lost when gain is applied.

Table 8. Output Gain Register

CHANNEL⁽¹⁾	REGISTER	FIELD [ BIT(S) ]	VALUES	EFFECTIVE RESOLUTION (BITS)	OUTPUT RANGE
All	RESET_DEV, addr 0x1C	OUTPUT_GAIN [ 10:9 ]	00 (default): Gain =1 (0 bits shift)	12	100% full scale
			01: Gain = 4 (2 bits left shift)	14	25% full scale
			10: Gain = 8 (3 bits left shift)	15	12.5% full scale
			11 : Gain = 16 (4 bits left shift)	16	6.25% full scale

(1) Channels 2 and 3 are available for LDC1314 only.

Example: If the conversion result for a channel is 0x07A3, with OUTPUT_GAIN=0x0, the reported output code is 0x07A. If OUTPUT_GAIN is set to 0x3 in the same condition, then the reported output code is 0x7A3. The original 4 MSBs (0x0) are no longer accessible. Figure 14 shows the segments of the 16-bit sample that is reported for each possible gain setting.

LDC1312-Q1 LDC1314-Q1 conversion_data_output_gain_snoscy9.gif

Figure 14. Conversion Data Output Gain

The sensor frequency can be determined by:

Equation 8. LDC1312-Q1 LDC1314-Q1 eq21_snoscy9.gif

where

DATAx = Conversion result from the DATA_CHx register
CHx_OFFSET = Offset value set in the OFFSET_CHx register
OUTPUT_GAIN = output multiplication factor set in the RESET_DEVICE.OUTPUT_GAIN register

8.3.3 Current Drive Control Registers

The registers listed in Table 9 are used to control the sensor drive current. The recommendations listed in the last column of Table 9 should be followed.

Auto-calibration mode is used to determine the optimal sensor drive current for a fixed sensor design. This mode should only be used during system prototyping.

The auto-amplitude correction attempts to maintain the sensor oscillation amplitude between 1.2V and 1.8V by adjusting the sensor drive current between conversions. When auto-amplitude correction is enabled, the output data may show non-monotonic behavior due to an adjustment in drive current. Auto-amplitude correction is only recommended for low-precision applications.

A high sensor current drive mode can be enabled to drive sensor coils with > 1.5mA on channel 0, only in single channel mode. This feature can be used when the sensor R_P is lower than 1kΩ. Set the HIGH_CURRENT_DRV register bit to b1 to enable this mode.

Table 9. Current Drive Control Registers

CHANNEL⁽¹⁾	REGISTER	FIELD [ BIT(S) ]	VALUE
All	CONFIG, addr 0x1A	SENSOR_ACTIVATE_SEL [11]	Sets current drive for sensor activation. Recommended value is b0 (Full Current mode).
		RP_OVERRIDE_EN [12]	Set to b1 for normal operation (RP over ride enabled)
		AUTO_AMP_DIS [10]	Disables Automatic amplitude correction. Set to b1 for normal operation (disabled)
0	CONFIG, addr 0x1A	HIGH_CURRENT_DRV [6]	b0 = normal current drive (1.5 mA) b1 = Increased current drive (> 1.5 mA) for Ch 0 in single channel mode only. Cannot be used in multi-channel mode.
0	DRIVE_CURRENT_CH0, addr 0x1E	CH0_IDRIVE [15:11]	Drive current used during the settling and conversion time for Ch. 0 (auto-amplitude correction must be disabled and RP over ride=1 )
0	DRIVE_CURRENT_CH0, addr 0x1E	CH0_INIT_IDRIVE [10:6]	Initial drive current stored during auto-calibration. Not used for normal operation.
1	DRIVE_CURRENT_CH1, addr 0x1F	CH1_IDRIVE [15:11]	Drive current used during the settling and conversion time for Ch. 1 (auto-amplitude correction must be disabled and RP over ride=1 )
1	DRIVE_CURRENT_CH1, addr 0x1F	CH1_INIT_IDRIVE [10:6]	Initial drive current stored during auto-calibration. Not used for normal operation.
2	DRIVE_CURRENT_CH2, addr 0x20	CH2_IDRIVE [15:11]	Drive current used during the settling and conversion time for Ch. 2 (auto-amplitude correction must be disabled and RP over ride=1 )
2	DRIVE_CURRENT_CH2, addr 0x20	CH2_INIT_IDRIVE [10:6]	Initial drive current stored during auto-calibration. Not used for normal operation.
3	DRIVE_CURRENT_CH3, addr 0x21	CH3_IDRIVE [15:11]	Drive current used during the settling and conversion time for Ch. 3 (auto-amplitude correction must be disabled and RP over ride=1 )
3	DRIVE_CURRENT_CH3, addr 0x21	CH3_INIT_IDRIVE [10:6]	Initial drive current stored during auto-calibration. Not used for normal operation.

(1) Channels 2 and 3 are available for LDC1314 only.

If the R_P value of the sensor attached to channel x is known, Table 10 can be used to select the 5-bit value to be programmed into the CHx_IDRIVE field for the channel. If the measured R_P (at maximum spacing between the sensor and the target) falls between two of the table values, use the current drive value associated with the lower R_P from Table 10. All channels that use an identical sensor/target configuration should use the same IDRIVE value.

Table 10. CHx_IDRIVE Values for Maximum Measured R_P.

MEASURED R_P (kΩ)	CHx_IDRIVE REGISTER FIELD VALUE, BINARY (BITS [15:11] )	NOMINAL CURRENT (μA)
90.0	b00000	16
77.6	b00001	18
66.9	b00010	20
57.6	b00011	23
49.7	b00100	28
42.8	b00101	32
36.9	b00110	40
31.8	b00111	46
27.4	b01000	52
23.3	b01001	59
20.4	b01010	72
17.6	b01011	82
15.1	b01100	95
13.0	b01101	110
11.2	b01110	127
9.7	b01111	146
8.4	b10000	169
7.2	b10001	195
6.2	b10010	212
5.4	b10011	244
4.6	b10100	297
4.0	b10101	342
3.4	b10110	424
3.0	b10111	489
2.5	b11000	551
2.2	b11001	635
1.9	b11010	763
1.6	b11011	880
1.4	b11100	1017
1.2	b11101	1173
1.0	b11110	1355
0.9	b11111	1563

If the R_P is not known, the following steps for auto-calibration can be used to configure the needed drive current, either during system prototyping, or during normal startup if feasible:

Set target at the maximum planned operating distance from the sensor.
Place the device into SLEEP mode by setting CONFIG.SLEEP_MODE_EN to b0.
Program the desired values of SETTLECOUNT and RCOUNT values for the channel.
Enable auto-calibration by setting RP_OVERDRIVE_EN to b0.
Take the device out of SLEEP mode by setting CONFIG.SLEEP_MODE_EN to b1.
Allow the device to perform at least one measurement, with the target stable (fixed) at the maximum operating range.
Read the channel current drive value from the appropriate DRIVE_CURRENT_CHx register (addresses 0x1e, 0x1f, 0x20, or 0x21), in the CHx_INIT_DRIVE field (bits 10:6). Save this value.
During startup for normal operating mode, write the value saved from the CHx_INIT_DRIVE bit field into the Chx_IDRIVE bit field (bits 15:11).
During normal operating mode, the RP_OVERRIDE_EN must set to b1 to force the fixed current drive.

If the current drive results in the oscillation amplitude greater than 1.8V, the internal ESD clamping circuit will become active. This may cause the sensor frequency to shift so that the output values no longer represent a valid system state. If the current drive is set at a lower value, the SNR performance of the system will decrease, and at near zero target range, oscillations may completely stop, and the output sample values will be all zeroes.

8.3.4 Device Status Registers

The registers listed in Table 11 may be used to read device status.

Table 11. Status Registers

CHANNEL⁽¹⁾	REGISTER	FIELDS [ BIT(S) ]	VALUES
All	STATUS, addr 0x18	12 fields are available that contain various status bits [ 15:0 ]	Refer to Register Maps section for a description of the individual status bits.
All	ERROR_CONFIG, addr 0x19	12 fields are available that are used to configure error reporting [ 15:0 ]	Refer to Register Maps section for a description of the individual error configuration bits.

(1) Channels 2 and 3 are available for LDC1314 only.

See the STATUS and ERROR_CONFIG register description in the Register Map section. These registers can be configured to trigger an interrupt on the INTB pin for certain events. The following conditions must be met:

The error or status register must be unmasked by enabling the appropriate register bit in the ERROR_CONFIG register
The INTB function must be enabled by setting CONFIG.INTB_DIS to 0

When a bit field in the STATUS register is set, the entire STATUS register content is held until read or until the DATA_CHx register is read. Reading also de-asserts INTB.

Interrupts are cleared by one of the following events:

Entering Sleep Mode
Power-on reset (POR)
Device enters Shutdown Mode (SD is asserted)
S/W reset
I2C read of the STATUS register: Reading the STATUS register will clear any error status bit set in STATUS along with the ERR_CHAN field and de-assert INTB

Setting register CONFIG.INTB_DIS to b1 disables the INTB function and holds the INTB pin high.

8.3.5 Input Deglitch Filter

The input deglitch filter suppresses EMI and ringing above the sensor frequency. It does not impact the conversion result as long as its bandwidth is configured to be above the maximum sensor frequency. The input deglitch filter can be configured in MUX_CONFIG.DEGLITCH register field as shown in Table 12. For optimal performance, TI recommends to select the lowest setting that exceeds the sensor oscillation frequency. For example, if the maximum sensor frequency is 2.0 MHz, choose MUX_CONFIG.DEGLITCH = b100 (3.3 MHz).

Table 12. Input deglitch filter register

CHANNEL⁽¹⁾	MUX_CONFIG.DEGLITCH REGISTER VALUE	DEGLITCH FREQEUNCY
ALL	001	1 MHz
ALL	100	3.3 MHz
ALL	101	10 MHz
ALL	011	33 MHz

(1) Channels 2 and 3 are available for LDC1314 only.

8.4 Device Functional Modes

8.4.1 Startup Mode

When the LDC powers up, it enters into Sleep Mode and will wait for configuration. Once the device is configured, exit Sleep Mode by setting CONFIG.SLEEP_MODE_EN to b0.

TI recommends to configure the LDC while in Sleep Mode. If a setting on the LDC needs to be changed, return the device to Sleep Mode, change the appropriate register, and then exit Sleep Mode.

8.4.2 Normal (Conversion) Mode

When operating in the normal (conversion) mode, the LDC is periodically sampling the frequency of the sensor(s) and generating sample outputs for the active channel(s).

8.4.3 Sleep Mode

Sleep Mode is entered by setting the CONFIG.SLEEP_MODE_EN register field to 1. While in this mode, the device configuration is maintained. To exit Sleep Mode, set the CONFIG.SLEEP_MODE_EN register field to 0. After setting CONFIG.SLEEP_MODE_EN to b0, sensor activation for the first conversion will begin after 16,384 f_INT clock cycles. While in Sleep Mode the I2C interface is functional so that register reads and writes can be performed. While in Sleep Mode, no conversions are performed. In addition, entering Sleep Mode will clear conversion results, any error condition and de-assert the INTB pin.

8.4.4 Shutdown Mode

When the SD pin is set to high, the LDC will enter Shutdown Mode. Shutdown Mode is the lowest power state. To exit Shutdown Mode, set the SD pin to low. Entering Shutdown Mode will return all registers to their default state.

While in Shutdown Mode, no conversions are performed. In addition, entering Shutdown Mode will clear any error condition and de-assert the INTB pin. While the device is in Shutdown Mode, is not possible to read to or write from the device via the I2C interface.

8.4.4.1 Reset

The LDC can be reset by writing to RESET_DEV.RESET_DEV. Any active conversion will stop and all register values will return to their default value. This register bit will always return 0b when read.

8.5 Programming

The LDC device uses an I2C interface to access control and data registers.

8.5.1 I2C Interface Specifications

The LDC uses an extended start sequence with I2C for register access. The maximum speed of the I2C interface is 400kbit/s. This sequence follows the standard I2C 7bit slave address followed by an 8bit pointer register byte to set the register address. When the ADDR pin is set low, the LDC I2C address is 0x2A; when the ADDR pin is set high, the LDC I2C address is 0x2B. The ADDR pin must not change state after the LDC exits Shutdown Mode.

LDC1312-Q1 LDC1314-Q1 td_I2C_write_reg_seq_snoscy9.gif

Figure 15. I2C Write Register Sequence

LDC1312-Q1 LDC1314-Q1 td_I2C_read_reg_seq_snoscy9.gif

Figure 16. I2C Read Register Sequence

8.6 Register Maps

8.6.1 Register List

Fields indicated with Reserved must be written only with indicated values, otherwise improper device operation may occur. The R/W column indicates the Read-Write status of the corresponding field. A ‘R/W’ entry indicates read and write capability, a ‘R’ indicates read-only, and a ‘W’ indicates write-only.

Figure 17. Register List

ADDRESS	NAME	DEFAULT VALUE	DESCRIPTION
0x00	DATA_CH0	0x0000	Channel 0 Conversion Result and Error Status
0x02	DATA_CH1	0x0000	Channel 1 Conversion Result and Error Status
0x04	DATA_CH2	0x0000	Channel 2 Conversion Result and Error Status (LDC1314 only)
0x06	DATA_CH3	0x0000	Channel 3 Conversion Result and Error Status (LDC1314 only)
0x08	RCOUNT_CH0	0x0080	Reference Count setting for Channel 0
0x09	RCOUNT_CH1	0x0080	Reference Count setting for Channel 1
0x0A	RCOUNT_CH2	0x0080	Reference Count setting for Channel 2. (LDC1314 only)
0x0B	RCOUNT_CH3	0x0080	Reference Count setting for Channel 3.(LDC1314 only)
0x0C	OFFSET_CH0	0x0000	Offset value for Channel 0
0x0D	OFFSET_CH1	0x0000	Offset value for Channel 1
0x0E	OFFSET_CH2	0x0000	Offset value for Channel 2 (LDC1314 only)
0x0F	OFFSET_CH3	0x0000	Offset value for Channel 3 (LDC1314 only)
0x10	SETTLECOUNT_CH0	0x0000	Channel 0 Settling Reference Count
0x11	SETTLECOUNT_CH1	0x0000	Channel 1 Settling Reference Count
0x12	SETTLECOUNT_CH2	0x0000	Channel 2 Settling Reference Count (LDC1314 only)
0x13	SETTLECOUNT_CH3	0x0000	Channel 3 Settling Reference Count (LDC1314 only)
0x14	CLOCK_DIVIDERS_CH0	0x0000	Reference and Sensor Divider settings for Channel 0
0x15	CLOCK_DIVIDERS_CH1	0x0000	Reference and Sensor Divider settings for Channel 1
0x16	CLOCK_DIVIDERS_CH2	0x0000	Reference and Sensor Divider settings for Channel 2 (LDC1314 only)
0x17	CLOCK_DIVIDERS_CH3	0x0000	Reference and Sensor Divider settings for Channel 3 (LDC1314 only)
0x18	STATUS	0x0000	Device Status Report
0x19	ERROR_CONFIG	0x0000	Error Reporting Configuration
0x1A	CONFIG	0x2801	Conversion Configuration
0x1B	MUX_CONFIG	0x020F	Channel Multiplexing Configuration
0x1C	RESET_DEV	0x0000	Reset Device
0x1E	DRIVE_CURRENT_CH0	0x0000	Channel 0 sensor current drive configuration
0x1F	DRIVE_CURRENT_CH1	0x0000	Channel 1 sensor current drive configuration
0x20	DRIVE_CURRENT_CH2	0x0000	Channel 2 sensor current drive configuration (LDC1314 only)
0x21	DRIVE_CURRENT_CH3	0x0000	Channel 3 sensor current drive configuration (LDC1314 only)
0x7E	MANUFACTURER_ID	0x5449	Manufacturer ID
0x7F	DEVICE_ID	0x3054	Device ID