ZHCSCX2E January   2014  – October 2017 LM15851

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     Device Images
      1. 16 倍抽取率 — 频谱响应 ƒS = 4GHz，FIN = 1897MHz（–1dBFS 时），ƒ(NCO_x) = 1827MHz
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Internal Characteristics
    8. 6.8 Switching Characteristics
    9. 6.9 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Signal Acquisition
      2. 7.3.2 The Analog Inputs
        1. 7.3.2.1 Input Clamp
        2. 7.3.2.2 AC Coupled Input Usage
        3. 7.3.2.3 DC Coupled Input Usage
        4. 7.3.2.4 Handling Single-Ended Input Signals
      3. 7.3.3 Clocking
      4. 7.3.4 Over-Range Function
      5. 7.3.5 ADC Core Features
        1. 7.3.5.1 The Reference Voltage
        2. 7.3.5.2 Common-Mode Voltage Generation
        3. 7.3.5.3 Bias Current Generation
        4. 7.3.5.4 Full Scale Range Adjust
        5. 7.3.5.5 Offset Adjust
        6. 7.3.5.6 Power-Down
        7. 7.3.5.7 Built-In Temperature Monitor Diode
      6. 7.3.6 Digital Down Converter (DDC)
        1. 7.3.6.1 NCO/Mixer
        2. 7.3.6.2 NCO Settings
          1. 7.3.6.2.1 NCO Frequency Phase Selection
          2. 7.3.6.2.2 NCO_0, NCO_1, and NCO_2 (NCO_x)
          3. 7.3.6.2.3 NCO_SEL Bits (2:0)
          4. 7.3.6.2.4 NCO Frequency Setting (Eight Total)
            1. 7.3.6.2.4.1 Basic NCO Frequency-Setting Mode
            2. 7.3.6.2.4.2 Rational NCO Frequency Setting Mode
          5. 7.3.6.2.5 NCO Phase-Offset Setting (Eight Total)
          6. 7.3.6.2.6 Programmable DDC Delay
        3. 7.3.6.3 Decimation Filters
        4. 7.3.6.4 DDC Output Data
        5. 7.3.6.5 Decimation Settings
          1. 7.3.6.5.1 Decimation Factor
          2. 7.3.6.5.2 DDC Gain Boost
      7. 7.3.7 Data Outputs
        1. 7.3.7.1 The Digital Outputs
        2. 7.3.7.2 JESD204B Interface Features and Settings
          1. 7.3.7.2.1  Scrambler Enable
          2. 7.3.7.2.2  Frames Per Multi-Frame (K-1)
          3. 7.3.7.2.3  DDR
          4. 7.3.7.2.4  JESD Enable
          5. 7.3.7.2.5  JESD Test Modes
          6. 7.3.7.2.6  Configurable Pre-Emphasis
          7. 7.3.7.2.7  Serial Output-Data Formatting
          8. 7.3.7.2.8  JESD204B Synchronization Features
          9. 7.3.7.2.9  SYSREF
          10. 7.3.7.2.10 SYNC~
          11. 7.3.7.2.11 Code-Group Synchronization
          12. 7.3.7.2.12 Multiple ADC Synchronization
    4. 7.4 Device Functional Modes
      1. 7.4.1 DDC Modes
      2. 7.4.2 Calibration
        1. 7.4.2.1 Foreground Calibration Mode
        2. 7.4.2.2 Background Calibration Mode
      3. 7.4.3 Timing Calibration Mode
      4. 7.4.4 Test-Pattern Modes
        1. 7.4.4.1 Serializer Test-Mode Details
        2. 7.4.4.2 PRBS Test Modes
        3. 7.4.4.3 Ramp Test Mode
        4. 7.4.4.4 Short and Long-Transport Test Mode
        5. 7.4.4.5 D21.5 Test Mode
        6. 7.4.4.6 K28.5 Test Mode
        7. 7.4.4.7 Repeated ILA Test Mode
        8. 7.4.4.8 Modified RPAT Test Mode
    5. 7.5 Programming
      1. 7.5.1 Using the Serial Interface
        1. 7.5.1.1 Streaming Mode
    6. 7.6 Register Map
      1. 7.6.1 Memory Map
      2. 7.6.2 Register Descriptions
        1. 7.6.2.1 Standard SPI-3.0 (0x000 to 0x00F)
          1. Table 34. Standard SPI-3.0 Registers
          2. 7.6.2.1.1  Configuration A Register (address = 0x000) [reset = 0x3C]
            1. Table 35. CFGA Field Descriptions
          3. 7.6.2.1.2  Configuration B Register (address = 0x001) [reset = 0x00]
            1. Table 36. CFGB Field Descriptions
          4. 7.6.2.1.3  Device Configuration Register (address = 0x002) [reset = 0x00]
            1. Table 37. DEVCFG Field Descriptions
          5. 7.6.2.1.4  Chip Type Register (address = 0x003) [reset = 0x03]
            1. Table 38. CHIP_TYPE Field Descriptions
          6. 7.6.2.1.5  Chip Version Register (address = 0x006) [reset = 0x13]
            1. Table 39. CHIP_VERSION Field Descriptions
          7. 7.6.2.1.6  Vendor Identification Register (address = 0x00C to 0x00D) [reset = 0x0451]
            1. Table 40. VENDOR_ID Field Descriptions
        2. 7.6.2.2 User SPI Configuration (0x010 to 0x01F)
          1. 7.6.2.2.1 User SPI Configuration Register (address = 0x010) [reset = 0x00]
            1. Table 42. USR0 Field Descriptions
        3. 7.6.2.3 General Analog, Bias, Band Gap, and Track and Hold (0x020 to 0x02F)
          1. 7.6.2.3.1 Power-On Reset Register (address = 0x021) [reset = 0x00]
            1. Table 44. POR Field Descriptions
          2. 7.6.2.3.2 I/O Gain 0 Register (address = 0x022) [reset = 0x40]
            1. Table 45. IO_GAIN_0 Field Descriptions
          3. 7.6.2.3.3 IO_GAIN_1 Register (address = 0x023) [reset = 0x00]
            1. Table 46. IO_GAIN_1 Field Descriptions
          4. 7.6.2.3.4 I/O Offset 0 Register (address = 0x025) [reset = 0x40]
            1. Table 47. IO_OFFSET_0 Field Descriptions
          5. 7.6.2.3.5 I/O Offset 1 Register (address = 0x026) [reset = 0x00]
            1. Table 48. IO_OFFSET_1 Field Descriptions
        4. 7.6.2.4 Clock (0x030 to 0x03F)
          1. 7.6.2.4.1 Clock Generator Control 0 Register (address = 0x030) [reset = 0xC0]
            1. Table 50. CLKGEN_0 Field Descriptions
          2. 7.6.2.4.2 Clock Generator Status Register (address = 0x031) [reset = 0x07]
            1. Table 51. CLKGEN_1 Field Descriptions
          3. 7.6.2.4.3 Clock Generator Control 2 Register (address = 0x032) [reset = 0x80]
            1. Table 52. CLKGEN_2 Field Descriptions
          4. 7.6.2.4.4 Analog Miscellaneous Register (address = 0x033) [reset = 0xC3]
            1. Table 53. ANA_MISC Field Descriptions
          5. 7.6.2.4.5 Input Clamp Enable Register (address = 0x034) [reset = 0x2F]
            1. Table 54. IN_CL_EN Field Descriptions
        5. 7.6.2.5 Serializer (0x040 to 0x04F)
          1. 7.6.2.5.1 Serializer Configuration Register (address = 0x040) [reset = 0x04]
            1. Table 56. SER_CFG Field Descriptions
        6. 7.6.2.6 ADC Calibration (0x050 to 0x1FF)
          1. 7.6.2.6.1 Calibration Configuration 0 Register (address = 0x050) [reset = 0x06]
            1. Table 58. CAL_CFG0 Field Descriptions
          2. 7.6.2.6.2 Calibration Configuration 1 Register (address = 0x051) [reset = 0xF4]
            1. Table 59. CAL_CFG1 Field Descriptions
          3. 7.6.2.6.3 Calibration Background Control Register (address = 0x057) [reset = 0x10]
            1. Table 60. CAL_BACK Field Descriptions
          4. 7.6.2.6.4 ADC Pattern and Over-Range Enable Register (address = 0x058) [reset = 0x00]
            1. Table 61. ADC_PAT_OVR_EN Field Descriptions
          5. 7.6.2.6.5 Calibration Vectors Register (address = 0x05A) [reset = 0x00]
            1. Table 62. CAL_VECTOR Field Descriptions
          6. 7.6.2.6.6 Calibration Status Register (address = 0x05B) [reset = undefined]
            1. Table 63. CAL_STAT Field Descriptions
          7. 7.6.2.6.7 Timing Calibration Register (address = 0x066) [reset = 0x02]
            1. Table 64. CAL_STAT Field Descriptions
        7. 7.6.2.7 Digital Down Converter and JESD204B (0x200-0x27F)
          1. 7.6.2.7.1  Digital Down-Converter (DDC) Control Register (address = 0x200) [reset = 0x10]
            1. Table 66. DDC_CTRL1 Field Descriptions
          2. 7.6.2.7.2  JESD204B Control 1 Register (address = 0x201) [reset = 0x0F]
            1. Table 67. JESD_CTRL1 Field Descriptions
          3. 7.6.2.7.3  JESD204B Control 2 Register (address = 0x202) [reset = 0x00]
            1. Table 68. JESD_CTRL2 Field Descriptions
          4. 7.6.2.7.4  JESD204B Device ID (DID) Register (address = 0x203) [reset = 0x00]
            1. Table 69. JESD_DID Field Descriptions
          5. 7.6.2.7.5  JESD204B Control 3 Register (address = 0x204) [reset = 0x00]
            1. Table 70. JESD_CTRL3 Field Descriptions
          6. 7.6.2.7.6  JESD204B and System Status Register (address = 0x205) [reset = Undefined]
            1. Table 71. JESD_STATUS Field Descriptions
          7. 7.6.2.7.7  Overrange Threshold 0 Register (address = 0x206) [reset = 0xF2]
            1. Table 72. OVR_T0 Field Descriptions
          8. 7.6.2.7.8  Overrange Threshold 1 Register (address = 0x207) [reset = 0xAB]
            1. Table 73. OVR_T1 Field Descriptions
          9. 7.6.2.7.9  Overrange Period Register (address = 0x208) [reset = 0x00]
            1. Table 74. OVR_N Field Descriptions
          10. 7.6.2.7.10 DDC Configuration Preset Mode Register (address = 0x20C) [reset = 0x00]
            1. Table 75. NCO_MODE Field Descriptions
          11. 7.6.2.7.11 DDC Configuration Preset Select Register (address = 0x20D) [reset = 0x00]
            1. Table 76. NCO_SEL Field Descriptions
          12. 7.6.2.7.12 Rational NCO Reference Divisor Register (address = 0x20E to 0x20F) [reset = 0x0000]
            1. Table 77. NCO_RDIV Field Descriptions
          13. 7.6.2.7.13 NCO Frequency (Preset x) Register (address = see ) [reset = see ]
            1. Table 78. NCO_FREQ_x Field Descriptions
          14. 7.6.2.7.14 NCO Phase (Preset x) Register (address = see ) [reset = see ]
            1. Table 79. NCO_PHASE_x Field Descriptions
          15. 7.6.2.7.15 DDC Delay (Preset x) Register (address = see ) [reset = see ]
            1. Table 80. DDC_DLY_x Field Descriptions
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 RF Sampling Receiver
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
    3. 8.3 Initialization Set-Up
      1. 8.3.1 JESD204B Startup Sequence
    4. 8.4 Dos and Don'ts
      1. 8.4.1 Common Application Pitfalls
  9. 9 Power Supply Recommendations
    1. 9.1 Supply Voltage
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Thermal Management
  11. 11器件和文档支持
    1. 11.1 器件支持
      1. 11.1.1 Third-Party Products Disclaimer
      2. 11.1.2 开发支持
      3. 11.1.3 器件命名规则
    2. 11.2 文档支持
      1. 11.2.1 相关文档
    3. 11.3 社区资源
    4. 11.4 商标
    5. 11.5 静电放电警告
    6. 11.6 Glossary
  12. 12机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

6.5 Electrical Characteristics

Unless otherwise noted, these specifications apply for V(VA12) = V(VD12) = 1.2 V, V(VA19) = 1.9 V, VIN full scale range at default setting (725 mVPP), VIN = –1 dBFS, differential AC-coupled sinewave input clock, ƒ(DEVCLK) = 4 GHz at 0.5 VPP with 50% duty cycle, R(RBIAS) = 3.3 kΩ ±0.1%, after a foreground (FG) mode calibration with timing calibration enabled. Typical values are at TA = 25°C.(1)(3)
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
DYNAMIC PERFORMANCE CHARACTERISTICS
IMD3 Third-order intermodulation distortion F1 = 2110 MHz at −13 dBFS
F2 = 2170 MHz at −13 dBFS		 –64 dBc
DECIMATE-BY-4 MODE
SNR1 Signal-to-noise ratio, integrated across DDC alias protected output bandwidth
Input frequency-dependent interleaving spurs included		 FIN = 600 MHz, –1 dBFS, decimate-by-4 mode TA = 25°C 59.9 dBFS
TA = TMIN to TMAX 56.2
TA = 25°C, calibration = BG 59.2
TA = TMIN to TMAX, calibration = BG 53.3
FIN = 2400 MHz, –1 dBFS, decimate-by-4 mode 56.4
SNR2 Signal-to-noise ratio, integrated across DDC alias protected output bandwidth
Input frequency-dependent interleaving spurs excluded		 FIN = 600 MHz, –1 dBFS, decimate-by-4 mode TA = 25°C(4) 60.1 dBFS
TA = TMIN to TMAX(4) 56.7
TA = 25°C, calibration = BG (4) 60.2
TA = TMIN to TMAX, calibration = BG(4) 56.7
FIN = 2400 MHz, –1 dBFS, decimate-by-4 mode(4) 57
SINAD1 Signal-to-noise and distortion ratio, integrated across DDC alias protected output bandwidth
Input frequency-dependent interleaving spurs included		 FIN = 600 MHz, –1 dBFS, decimate-by-4 mode TA = 25°C 59.9 dBFS
TA = TMIN to TMAX 55.9
TA = 25°C, calibration = BG 59.2
TA = TMIN to TMAX, calibration = BG 53.1
FIN = 2400 MHz, –1 dBFS, decimate-by-4 mode 56.4
SINAD2 Signal-to-noise and distortion ratio, integrated across DDC alias protected output bandwidth
Interleaving spurs excluded		 FIN = 600 MHz, –1 dBFS, decimate-by-4 mode TA = 25°C(4) 60.1 dBFS
TA = TMIN to TMAX(4) 56.3
TA = 25°C, calibration = BG (4) 60.1
TA = TMIN to TMAX, calibration = BG(4) 56.4
FIN = 2400 MHz, –1 dBFS, decimate-by-4 mode(4) 57
ENOB1 Effective number of bits, integrated across DDC alias protected output bandwidth
Interleaving spurs included		 FIN = 600 MHz, –1 dBFS, Decimate-by-4 mode TA = 25°C 9.7 Bits
TA = TMIN to TMAX 9.0
TA = 25°C, calibration = BG 9.5
TA = TMIN to TMAX, calibration = BG 8.5
FIN = 2400 MHz, –1 dBFS, decimate-by-4 mode 9.1
ENOB2 Effective number of bits, integrated across DDC alias protected output bandwidth
Interleaving spurs excluded		 FIN = 600 MHz, –1 dBFS, decimate-by-4 mode TA = 25°C(4) 9.7 Bits
TA = TMIN to TMAX(4) 9.0
TA = 25°C, calibration = BG (4) 9.7
TA = TMIN to TMAX, calibration = BG(4) 9.1
FIN = 2400 MHz, –1 dBFS, decimate-by-4 mode(4) 8.5
SFDR1 Spurious-free dynamic range across entire Nyquist bandwidth
Interleaving spurs included		 FIN = 600 MHz, –1 dBFS, decimate-by-4 mode TA = 25°C 70.1 dBFS
TA = TMIN to TMAX 59.2
TA = 25°C, calibration = BG 62.9
TA = TMIN to TMAX, calibration = BG 51.8
FIN = 2400 MHz, –1 dBFS, decimate-by-4 mode 66.4
SFDR2 Spurious-free dynamic range across entire Nyquist bandwidth
Interleaving spurs excluded		 FIN = 600 MHz, –1 dBFS, decimate-by-4 mode TA = 25°C(4) 71.6 dBFS
TA = TMIN to TMAX(4) 60
TA = 25°C, calibration = BG (4) 74.8
TA = TMIN to TMAX, calibration = BG(4) 62.9
FIN = 2400 MHz, –1 dBFS, Decimate-by-4 mode(4) 80.4
ƒS/2 Interleaving offset spur at ½ sampling rate(5) FIN = 600 MHz, –1 dBFS, decimate-by-4 mode TA = 25°C –72 dBFS
TA = TMIN to TMAX –56
TA = 25°C, calibration = BG –65
TA = TMIN to TMAX, calibration = BG –50.5
ƒS/4 Interleaving offset spur at ¼ sampling rate(5) FIN = 600 MHz, –1 dBFS, decimate-by-4 mode TA = 25°C –68 dBFS
TA = TMIN to TMAX –55
TA = 25°C, calibration = BG –62
TA = TMIN to TMAX, calibration = BG –47.4
ƒS/2 – FIN Interleaving spur at ½ sampling rate – input frequency(5) FIN = 600 MHz, –1 dBFS, decimate-by-4 mode TA = 25°C –75 dBFS
TA = TMIN to TMAX –62.3
TA = 25°C, calibration = BG –70
TA = TMIN to TMAX, calibration = BG –51.5
ƒS/4 + FIN Interleaving spur at ¼ sampling rate + input frequency(5) FIN = 600 MHz, –1 dBFS, decimate-by-4 mode TA = 25°C –73 dBFS
TA = TMIN to TMAX –58.9
TA = 25°C, calibration = BG –65
TA = TMIN to TMAX, calibration = BG –52.8
ƒS/4 – FIN Interleaving spur at ¼ sampling rate – input frequency(5) FIN = 600 MHz, –1 dBFS, Decimate-by-4 mode TA = 25°C –78 dBFS
TA = TMIN to TMAX –60.4
TA = 25°C, calibration = BG –65
TA = TMIN to TMAX, calibration = BG –52.3
THD Total harmonic distortion(5) FIN = 600 MHz, –1 dBFS, decimate-by-4 mode TA = 25°C –70 dBFS
TA = TMIN to TMAX –59.5
TA = 25°C, calibration = BG –73
TA = TMIN to TMAX, calibration = BG –60
HD2 Second harmonic distortion(5) FIN = 600 MHz, –1 dBFS, decimate-by-4 mode TA = 25°C –83 dBFS
TA = TMIN to TMAX –62
TA = 25°C, calibration = BG –78
TA = TMIN to TMAX, calibration = BG –62.5
HD3 Third harmonic distortion(5) FIN = 600 MHz, –1 dBFS, decimate-by-4 mode TA = 25°C –72 dBFS
TA = TMIN to TMAX –59.5
TA = 25°C, calibration = BG –82
TA = TMIN to TMAX, calibration = BG –62
DECIMATE-BY-8 MODE
SNR1 Signal-to-noise ratio, integrated across DDC output bandwidth
Interleaving spurs included		 FIN = 600 MHz, –1 dBFS, decimate-by-8 mode 63 dBFS
Calibration = BG 61.6
FIN = 2400 MHz, –1 dBFS, decimate-by-8 mode 54.6
SNR2 Signal-to-noise ratio, integrated across DDC output bandwidth
Interleaving spurs excluded		 FIN = 600 MHz, –1 dBFS, decimate-by-8 mode(4) 63.3 dBFS
Calibration = BG 63.3
SINAD1 Signal-to-noise and distortion ratio, integrated across DDC output bandwidth
Interleaving spurs included		 FIN = 600 MHz, –1 dBFS, Decimate-by-8 mode 63 dBFS
Calibration = BG 61.6
FIN = 2400 MHz, –1 dBFS, decimate-by-8 mode 54.6
SINAD2 Signal-to-noise and distortion ratio, integrated across DDC output bandwidth
Interleaving spurs excluded		 FIN = 600 MHz, –1 dBFS, decimate-by-8 mode(4) 63.3 dBFS
Calibration = BG 63.3
ENOB1 Effective number of bits, integrated across DDC output bandwidth
Interleaving spurs included		 FIN = 600 MHz, –1 dBFS, decimate-by-8 mode 10.2 Bits
Calibration = BG 10.0
FIN = 2400 MHz, –1 dBFS, decimate-by-8 mode 8.8
ENOB2 Effective number of bits, integrated across DDC output bandwidth
Interleaving spurs excluded		 FIN = 600 MHz, –1 dBFS, decimate-by-8 mode(5) 10.2 Bits
Calibration = BG 10.2
SFDR1 Spurious-free dynamic range
Interleaving Spurs Included		 FIN = 600 MHz, –1 dBFS, decimate-by-8 mode 74.9 dBFS
Calibration = BG 68.3
SFDR2 Spurious-free dynamic range
Interleaving spurs excluded		 FIN = 600 MHz, –1 dBFS, decimate-by-8 mode(5) 77.8 dBFS
Calibration = BG 77.8
ƒS/2 Interleaving offset spur at ½ sampling rate(5) FIN = 600 MHz, –1 dBFS, decimate-by-8 mode –73 dBFS
Calibration = BG –72
ƒS/4 Interleaving offset spur at ¼ sampling rate(5) FIN = 600 MHz, –1 dBFS, decimate-by-8 mode –70 dBFS
Calibration = BG –66
ƒS/2 – FIN Interleaving spur at ½ sampling rate – input frequency(5) FIN = 600 MHz, –1 dBFS, decimate-by-8 mode –76 dBFS
Calibration = BG –67
ƒS/4 + FIN Interleaving spur at ¼ sampling rate + input frequency(5) FIN = 600 MHz, –1 dBFS, decimate-by-8 mode –72 dBFS
Calibration = BG –64
ƒS/4 – FIN Interleaving spur at ¼ sampling rate – input frequency(5) FIN = 600 MHz, –1 dBFS, decimate-by-8 mode –74 dBFS
Calibration = BG –67
THD Total harmonic distortion(6) FIN = 600 MHz, –1 dBFS, decimate-by-8 mode –70 dBFS
Calibration = BG –72
FIN = 2400 MHz, –1 dBFS, decimate-by-8 mode –71
HD2 Second harmonic distortion(6) FIN = 600 MHz, –1 dBFS, decimate-by-8 mode –80 dBFS
Calibration = BG –79
FIN = 2400 MHz, –1 dBFS, decimate-by-8 mode –78
HD3 Third harmonic distortion(6) FIN = 600 MHz, –1 dBFS, decimate-by-8 mode –74 dBFS
Calibration = BG –80
FIN = 2400 MHz, –1 dBFS, decimate-by-8 mode –-77
DDC CHARACTERISTICS
Alias protection(2) 80 dB
Alias protected bandwidth(2) 80 % of output BW
SFDR-DDC Spurious-free dynamic range of digital down-converter(2) 100 dB
Implementation loss(2) 0.5 dB
ANALOG INPUT CHARACTERISTICS
VID(VIN) Full-scale analog-differential input range Minimum FSR setting(6) 500 mVPP
Default FSR setting, TA = TMIN to TMAX 650 725 800
Maximum FSR setting(6) 950
CI(VIN) Analog input capacitance(2) Differential 0.05 pF
Each input pin to ground 1.5 pF
RID(VIN) Differential input resistance 80 95 110 Ω
FPBW Full power bandwidth –3 dB — calibration = BG 2.8 GHz
–3 dB — calibration = FG 3.2
Gain flatness DC to 2 GHz 1.2 dB
2 GHz to 4 GHz 3.8
DC to 2 GHz — calibration = BG 1.5
2 GHz to 4 GHz — calibration = BG 4.5
ANALOG OUTPUT CHARACTERISTICS (VCMO, VBG)
V(VCMO) Common-mode output voltage I(VCMO) = ±100 µA, TA = 25°C 1.225 V
I(VCMO) = ±100 µA, TA = TMIN to TMAX 1.185 1.265
TCVO(VCMO) Common-mode output-voltage temperature coefficient TA = TMIN to TMAX -21 ppm/°C
C(LOAD_VCMO) Maximum VCMO output load capacitance 80 pF
VO(BG) Bandgap reference output voltage I(BG) = ±100 µA, TA = 25°C 1.248 V
I(BG) = ±100 µA, TA = TMIN to TMAX 1.195 1.3
TCVref(BG) Bandgap reference voltage temperature coefficient TA = TMIN to TMAX,
I(BG) = ±100 µA		 0 ppm/°C
C(LOAD_BG) Maximum bandgap reference output load capacitance 80 pF
TEMPERATURE DIODE CHARACTERISTICS
V(TDIODE) Temperature diode voltage slope Offset voltage (approx. 0.77 V) varies with process and must be measured for each part. Offset measurement should be done with PowerDown=1 to minimize device self-heating. 100-µA forward current
Device active		 –1.6 mV/°C
100-µA forward current
Device in power-down		 –1.6 mV/°C
CLOCK INPUT CHARACTERISTICS (DEVCLK±, SYSREF±, SYNC~)
VID(CLK) Differential clock input level Sine wave clock, TA = TMIN to TMAX 0.4 0.6 2 VPP
Square wave clock, TA = TMIN to TMAX 0.4 0.6 2 VPP
II(CLK) Input current VI = 0 or VI = VA ±1 µA
CI(CLK) Input capacitance(2) Differential 0.02 pF
Each input to ground 1 pF
RID(CLK) Differential input resistance TA = 25°C 95 Ω
TA = TMIN to TMAX 80 110 Ω
CML OUTPUT CHARACTERISTICS (DS0–DS7±)
VOD Differential output voltage Assumes ideal 100-Ω load
Measured differentially
Default pre-emphasis setting		 280 305 330 mV peak
VO(ofs) Output offset voltage 0.6 V
IOS Output short-circuit current Output+ and output– shorted together ±6 mA
Output+ or output– shorted to 0 V 12
ZOD Differential output impedance 100 Ω
LVCMOS INPUT CHARACTERISTICS (SDI, SCLK, SCS, SYNC~)
VIH Logic high input voltage See (6) 0.83 V
VIL Logic low input voltage See (6) 0.4 V
CI Input capacitance(2)(7) Each input to ground 1 pF
LVCMOS OUTPUT CHARACTERISTICS (SDO, OR_T0, OR_T1)
VOH CMOS H level output IOH = –400 µA(6) 1.65 1.9 V
VOL CMOS L level output IOH = 400 µA(6) 0.01 0.15 V
POWER SUPPLY CHARACTERISTICS
I(VA19) Analog 1.9-V supply current PD = 0, calibration = BG, decimate by 8, DDR = 0, P54 = 1 560 607 mA
I(VA12) Analog 1.2-V supply current PD = 0, calibration = BG, decimate by 8, DDR = 0, P54 = 1 377 428 mA
I(VD12) Digital 1.2-V supply current PD = 0, calibration = BG, decimate by 8, DDR = 0, P54 = 1 541 826 mA
PC Power consumption PD = 0, calibration = BG, decimate by 8, DDR = 0, P54 = 1 2.17 2.66 W
PD = 1 < 50 mW
(1) To ensure accuracy, the VA19, VA12, and VD12 pins are required to be well bypassed. Each supply pin must be decoupled with one or more bypass capacitors.
(2) This parameter is specified by design and is not tested in production.
(3) Interleave related fixed frequency spurs at ƒS / 4 and ƒS / 2 are excluded from all SNR, SINAD, ENOB and SFDR specifications. The magnitude of these spurs is provided separately.
(4) Interleave related spurs at ƒS / 2 – FIN, ƒS / 4 + FIN and ƒS / 4 – FIN are excluded from these performance calculations. The magnitude of these spurs is provided separately.
(5) Magnitude of reported tones in output spectrum of ADC core. This tone will only be present in the DDC output for specific Decimation and NCO settings. Careful frequency planning can be used to intentionally place unwanted tones outside the DDC output spectrum.
(6) This parameter is specified by design, characterization, or both and is not tested in production.
(7) The digital control pin capacitances are die capacitances only and is in addition to package and bond-wire capacitance of approximately 0.4 pF.
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