ZHCSCX2E January 2014 – October 2017 LM15851
PRODUCTION DATA.
The second function for the SYSREF input is to facilitate the precise synchronization of multiple ADCs in a system.
One key challenge is to ensure that this synchronization works is to ensure that the SYSREF inputs are repeatedly captured by the input CLK. Two key elements must occur for the SYSREF inputs to be captured. First, the SYSREF input must be created so that it is synchronous to the input DEVCLK, be an integer sub-harmonic of the multi-frame (K × t(FRAME)) and a repeatable and fixed-phase offset. When this constraint is achieved, repeatedly capturing SYSREF is easier. To further ease this task, the SYSREF signal is routed through a user-adjustable delay which eases the timing requirements with respect to the input DEVCLK signal. The SYSREF delay RDEL is adjusted through bits 3 through 0 in register 0x032.
As long as the SYSREF signal has a fixed timing relationship to DEVCLK, the internal delay can be used to maximize the setup and hold times between the internally delayed SYSREF and the internal DEVCLK signal. These timing relationships are listed in the Timing Requirements table. To find the proper delay setting, the RDEL value is adjusted from minimum to maximum while applying SYSREF and monitoring the SysRefDet and Dirty Capture detect bits. The SysRefDet bit is set whenever a rising edge of SYSREF is detected. The Dirty Capture bit is set whenever the setup or hold time between DEVCLK and the delayed SYSREF is insufficient. The SysRefDetClr bit is used to clear the SysRefDet bit. The Clear Dirty Capture bit is used to clear that bit.
This procedure should be followed to determine the range of delay settings where a clean SYSREF capture is achieved. The delay value at the center of the clean capture range must be loaded as the final RDEL setting. Table 29 lists a summary of the control bits that are used and the monitor bits that are read.
| BIT NAME | REGISTER ADDRESS | REGISTER BIT | FUNCTION |
|---|---|---|---|
| RDEL | 0x032 | 3:0 | Adjust relative delay between DEVCLK and SYSREF |
| SysRefDet | 0x031 | 7 | Detect if a SYSREF rising edge has been captured (not self clearing) |
| Dirty Capture | 0x031 | 6 | Detect if SYSREF rising edge capture failed setup/hold (not self clearing) |
| SysRefDetClr | 0x030 | 5 | Clear SYSREF detection bit |
| Clear Dirty Capture | 0x030 | 4 | Clear Dirty Capture detection bit |
| SysRef_Rcvr_En | 0x030 | 7 | Enable SYSREF receiver. See the CLKGEN_0 descriptions in the Clock Generator Control 0 Register section for more information. |
| SysRef_Pr_En | 0x030 | 6 | Enable SYSREF processing. See the CLKGEN_0 descriptions in the Clock Generator Control 0 Register section for more information. |
One final aspect of multi-device synchronization relates to phase alignment of the NCO phase accumulators when DDC modes are enabled. The NCO phase accumulators are reset during the ILA phase of link startup which means that for multiple ADCs to have NCO phase alignment, all links must be enabled in the same LMFC period. Enabling all links in the same LMFC period requires synchronizing the SYNC~ de-assertion across all data receivers in the system, so that all of the SYNC~ signals are released during the same LMFC period. Using large K values and resulting longer LMFC periods will ease this task, at the expense of potentially higher latency in the receiving device.