ZHCSCX2E January   2014  – October 2017 LM15851

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     Device Images
      1. 16 倍抽取率 — 频谱响应 ƒS = 4GHz，FIN = 1897MHz（–1dBFS 时），ƒ(NCO_x) = 1827MHz
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Internal Characteristics
    8. 6.8 Switching Characteristics
    9. 6.9 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Signal Acquisition
      2. 7.3.2 The Analog Inputs
        1. 7.3.2.1 Input Clamp
        2. 7.3.2.2 AC Coupled Input Usage
        3. 7.3.2.3 DC Coupled Input Usage
        4. 7.3.2.4 Handling Single-Ended Input Signals
      3. 7.3.3 Clocking
      4. 7.3.4 Over-Range Function
      5. 7.3.5 ADC Core Features
        1. 7.3.5.1 The Reference Voltage
        2. 7.3.5.2 Common-Mode Voltage Generation
        3. 7.3.5.3 Bias Current Generation
        4. 7.3.5.4 Full Scale Range Adjust
        5. 7.3.5.5 Offset Adjust
        6. 7.3.5.6 Power-Down
        7. 7.3.5.7 Built-In Temperature Monitor Diode
      6. 7.3.6 Digital Down Converter (DDC)
        1. 7.3.6.1 NCO/Mixer
        2. 7.3.6.2 NCO Settings
          1. 7.3.6.2.1 NCO Frequency Phase Selection
          2. 7.3.6.2.2 NCO_0, NCO_1, and NCO_2 (NCO_x)
          3. 7.3.6.2.3 NCO_SEL Bits (2:0)
          4. 7.3.6.2.4 NCO Frequency Setting (Eight Total)
            1. 7.3.6.2.4.1 Basic NCO Frequency-Setting Mode
            2. 7.3.6.2.4.2 Rational NCO Frequency Setting Mode
          5. 7.3.6.2.5 NCO Phase-Offset Setting (Eight Total)
          6. 7.3.6.2.6 Programmable DDC Delay
        3. 7.3.6.3 Decimation Filters
        4. 7.3.6.4 DDC Output Data
        5. 7.3.6.5 Decimation Settings
          1. 7.3.6.5.1 Decimation Factor
          2. 7.3.6.5.2 DDC Gain Boost
      7. 7.3.7 Data Outputs
        1. 7.3.7.1 The Digital Outputs
        2. 7.3.7.2 JESD204B Interface Features and Settings
          1. 7.3.7.2.1  Scrambler Enable
          2. 7.3.7.2.2  Frames Per Multi-Frame (K-1)
          3. 7.3.7.2.3  DDR
          4. 7.3.7.2.4  JESD Enable
          5. 7.3.7.2.5  JESD Test Modes
          6. 7.3.7.2.6  Configurable Pre-Emphasis
          7. 7.3.7.2.7  Serial Output-Data Formatting
          8. 7.3.7.2.8  JESD204B Synchronization Features
          9. 7.3.7.2.9  SYSREF
          10. 7.3.7.2.10 SYNC~
          11. 7.3.7.2.11 Code-Group Synchronization
          12. 7.3.7.2.12 Multiple ADC Synchronization
    4. 7.4 Device Functional Modes
      1. 7.4.1 DDC Modes
      2. 7.4.2 Calibration
        1. 7.4.2.1 Foreground Calibration Mode
        2. 7.4.2.2 Background Calibration Mode
      3. 7.4.3 Timing Calibration Mode
      4. 7.4.4 Test-Pattern Modes
        1. 7.4.4.1 Serializer Test-Mode Details
        2. 7.4.4.2 PRBS Test Modes
        3. 7.4.4.3 Ramp Test Mode
        4. 7.4.4.4 Short and Long-Transport Test Mode
        5. 7.4.4.5 D21.5 Test Mode
        6. 7.4.4.6 K28.5 Test Mode
        7. 7.4.4.7 Repeated ILA Test Mode
        8. 7.4.4.8 Modified RPAT Test Mode
    5. 7.5 Programming
      1. 7.5.1 Using the Serial Interface
        1. 7.5.1.1 Streaming Mode
    6. 7.6 Register Map
      1. 7.6.1 Memory Map
      2. 7.6.2 Register Descriptions
        1. 7.6.2.1 Standard SPI-3.0 (0x000 to 0x00F)
          1. Table 34. Standard SPI-3.0 Registers
          2. 7.6.2.1.1  Configuration A Register (address = 0x000) [reset = 0x3C]
            1. Table 35. CFGA Field Descriptions
          3. 7.6.2.1.2  Configuration B Register (address = 0x001) [reset = 0x00]
            1. Table 36. CFGB Field Descriptions
          4. 7.6.2.1.3  Device Configuration Register (address = 0x002) [reset = 0x00]
            1. Table 37. DEVCFG Field Descriptions
          5. 7.6.2.1.4  Chip Type Register (address = 0x003) [reset = 0x03]
            1. Table 38. CHIP_TYPE Field Descriptions
          6. 7.6.2.1.5  Chip Version Register (address = 0x006) [reset = 0x13]
            1. Table 39. CHIP_VERSION Field Descriptions
          7. 7.6.2.1.6  Vendor Identification Register (address = 0x00C to 0x00D) [reset = 0x0451]
            1. Table 40. VENDOR_ID Field Descriptions
        2. 7.6.2.2 User SPI Configuration (0x010 to 0x01F)
          1. 7.6.2.2.1 User SPI Configuration Register (address = 0x010) [reset = 0x00]
            1. Table 42. USR0 Field Descriptions
        3. 7.6.2.3 General Analog, Bias, Band Gap, and Track and Hold (0x020 to 0x02F)
          1. 7.6.2.3.1 Power-On Reset Register (address = 0x021) [reset = 0x00]
            1. Table 44. POR Field Descriptions
          2. 7.6.2.3.2 I/O Gain 0 Register (address = 0x022) [reset = 0x40]
            1. Table 45. IO_GAIN_0 Field Descriptions
          3. 7.6.2.3.3 IO_GAIN_1 Register (address = 0x023) [reset = 0x00]
            1. Table 46. IO_GAIN_1 Field Descriptions
          4. 7.6.2.3.4 I/O Offset 0 Register (address = 0x025) [reset = 0x40]
            1. Table 47. IO_OFFSET_0 Field Descriptions
          5. 7.6.2.3.5 I/O Offset 1 Register (address = 0x026) [reset = 0x00]
            1. Table 48. IO_OFFSET_1 Field Descriptions
        4. 7.6.2.4 Clock (0x030 to 0x03F)
          1. 7.6.2.4.1 Clock Generator Control 0 Register (address = 0x030) [reset = 0xC0]
            1. Table 50. CLKGEN_0 Field Descriptions
          2. 7.6.2.4.2 Clock Generator Status Register (address = 0x031) [reset = 0x07]
            1. Table 51. CLKGEN_1 Field Descriptions
          3. 7.6.2.4.3 Clock Generator Control 2 Register (address = 0x032) [reset = 0x80]
            1. Table 52. CLKGEN_2 Field Descriptions
          4. 7.6.2.4.4 Analog Miscellaneous Register (address = 0x033) [reset = 0xC3]
            1. Table 53. ANA_MISC Field Descriptions
          5. 7.6.2.4.5 Input Clamp Enable Register (address = 0x034) [reset = 0x2F]
            1. Table 54. IN_CL_EN Field Descriptions
        5. 7.6.2.5 Serializer (0x040 to 0x04F)
          1. 7.6.2.5.1 Serializer Configuration Register (address = 0x040) [reset = 0x04]
            1. Table 56. SER_CFG Field Descriptions
        6. 7.6.2.6 ADC Calibration (0x050 to 0x1FF)
          1. 7.6.2.6.1 Calibration Configuration 0 Register (address = 0x050) [reset = 0x06]
            1. Table 58. CAL_CFG0 Field Descriptions
          2. 7.6.2.6.2 Calibration Configuration 1 Register (address = 0x051) [reset = 0xF4]
            1. Table 59. CAL_CFG1 Field Descriptions
          3. 7.6.2.6.3 Calibration Background Control Register (address = 0x057) [reset = 0x10]
            1. Table 60. CAL_BACK Field Descriptions
          4. 7.6.2.6.4 ADC Pattern and Over-Range Enable Register (address = 0x058) [reset = 0x00]
            1. Table 61. ADC_PAT_OVR_EN Field Descriptions
          5. 7.6.2.6.5 Calibration Vectors Register (address = 0x05A) [reset = 0x00]
            1. Table 62. CAL_VECTOR Field Descriptions
          6. 7.6.2.6.6 Calibration Status Register (address = 0x05B) [reset = undefined]
            1. Table 63. CAL_STAT Field Descriptions
          7. 7.6.2.6.7 Timing Calibration Register (address = 0x066) [reset = 0x02]
            1. Table 64. CAL_STAT Field Descriptions
        7. 7.6.2.7 Digital Down Converter and JESD204B (0x200-0x27F)
          1. 7.6.2.7.1  Digital Down-Converter (DDC) Control Register (address = 0x200) [reset = 0x10]
            1. Table 66. DDC_CTRL1 Field Descriptions
          2. 7.6.2.7.2  JESD204B Control 1 Register (address = 0x201) [reset = 0x0F]
            1. Table 67. JESD_CTRL1 Field Descriptions
          3. 7.6.2.7.3  JESD204B Control 2 Register (address = 0x202) [reset = 0x00]
            1. Table 68. JESD_CTRL2 Field Descriptions
          4. 7.6.2.7.4  JESD204B Device ID (DID) Register (address = 0x203) [reset = 0x00]
            1. Table 69. JESD_DID Field Descriptions
          5. 7.6.2.7.5  JESD204B Control 3 Register (address = 0x204) [reset = 0x00]
            1. Table 70. JESD_CTRL3 Field Descriptions
          6. 7.6.2.7.6  JESD204B and System Status Register (address = 0x205) [reset = Undefined]
            1. Table 71. JESD_STATUS Field Descriptions
          7. 7.6.2.7.7  Overrange Threshold 0 Register (address = 0x206) [reset = 0xF2]
            1. Table 72. OVR_T0 Field Descriptions
          8. 7.6.2.7.8  Overrange Threshold 1 Register (address = 0x207) [reset = 0xAB]
            1. Table 73. OVR_T1 Field Descriptions
          9. 7.6.2.7.9  Overrange Period Register (address = 0x208) [reset = 0x00]
            1. Table 74. OVR_N Field Descriptions
          10. 7.6.2.7.10 DDC Configuration Preset Mode Register (address = 0x20C) [reset = 0x00]
            1. Table 75. NCO_MODE Field Descriptions
          11. 7.6.2.7.11 DDC Configuration Preset Select Register (address = 0x20D) [reset = 0x00]
            1. Table 76. NCO_SEL Field Descriptions
          12. 7.6.2.7.12 Rational NCO Reference Divisor Register (address = 0x20E to 0x20F) [reset = 0x0000]
            1. Table 77. NCO_RDIV Field Descriptions
          13. 7.6.2.7.13 NCO Frequency (Preset x) Register (address = see ) [reset = see ]
            1. Table 78. NCO_FREQ_x Field Descriptions
          14. 7.6.2.7.14 NCO Phase (Preset x) Register (address = see ) [reset = see ]
            1. Table 79. NCO_PHASE_x Field Descriptions
          15. 7.6.2.7.15 DDC Delay (Preset x) Register (address = see ) [reset = see ]
            1. Table 80. DDC_DLY_x Field Descriptions
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 RF Sampling Receiver
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
    3. 8.3 Initialization Set-Up
      1. 8.3.1 JESD204B Startup Sequence
    4. 8.4 Dos and Don'ts
      1. 8.4.1 Common Application Pitfalls
  9. 9 Power Supply Recommendations
    1. 9.1 Supply Voltage
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Thermal Management
  11. 11器件和文档支持
    1. 11.1 器件支持
      1. 11.1.1 Third-Party Products Disclaimer
      2. 11.1.2 开发支持
      3. 11.1.3 器件命名规则
    2. 11.2 文档支持
      1. 11.2.1 相关文档
    3. 11.3 社区资源
    4. 11.4 商标
    5. 11.5 静电放电警告
    6. 11.6 Glossary
  12. 12机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

7.6.1 Memory Map

Address ResetTypeRegister
Standard SPI-3.0 (0x000 to 0x00F)
0x000 0x3C R/W Configuration A Register
0x001 0x00 R Configuration B Register
0x002 0x00 R/W Device Configuration Register
0x003 0x03 R Chip Type Register
0x004-0x005 Undefined R RESERVED
0x006 0x13 R Chip Version Register
0x007-0x00B Undefined R RESERVED
0x00C-0x00D 0x0451 R Vendor Identification Register
0x00E-0x00F Undefined R RESERVED
User SPI Configuration (0x010 to 0x01F)
0x010 0x00 R/W User SPI Configuration Register
0x011-0x01F Undefined R RESERVED
General Analog, Bias, Band Gap, and Track and Hold (0x020 to 0x02F)
0x020 0x9D R/W RESERVED
0x021 0x00 R/W Power-On Reset Register
0x022 0x40 R/W I/O Gain 0 Register
0x023 0x00 R/W I/O Gain 1 Register
0x024 0x00 R/W RESERVED
0x025 0x40 R/W I/O Offset 0 Register
0x026 0x00 R/W I/O Offset 1 Register
0x027 0x06 R/W RESERVED
0x028 0xBA R/W RESERVED
0x029 0xD4 R/W RESERVED
0x02A 0xEA R/W RESERVED
0x02B-0x02F Undefined R RESERVED
Clock (0x030 to 0x03F)
0x030 0xC0 R/W Clock Generator Control 0 Register
0x031 0x07 R Clock Generator Status Register
0x032 0x80 R/W Clock Generator Control 2 Register
0x033 0xC3 R/W Analog Miscellaneous Register
0x034 0x2F R/W Input Clamp Enable Register
0x035 0xDF R/W RESERVED
0x036 0x00 R/W RESERVED
0x037 0x45 R/W RESERVED
0x038-0x03F Undefined R/W RESERVED
Serializer (0x040 to 0x04F)
0x040 0x04 R/W Serializer Configuration Register
0x041-0x04F Undefined R RESERVED
ADC Calibration (0x050 to 0x1FF)
0x050 0x06 R/W Calibration Configuration 0 Register
0x051 0xF4 R/W Calibration Configuration 1 Register
0x052 0x00 R/W RESERVED
0x053 0x5C R/W RESERVED
0x054 0x1C R/W RESERVED
0x055 0x92 R/W RESERVED
0x056 0x20 R/W RESERVED
0x057 0x10 R/W Calibration Background Control Register
0x058 0x00 R/W ADC Pattern and Over-Range Enable Register
0x059 0x00 R/W RESERVED
0x05A 0x00 R/W Calibration Vectors Register
0x05B Undefined R Calibration Status Register
0x05C 0x00 R/W RESERVED
0x05D-0x05E Undefined R/W RESERVED
0x05F 0x00 R/W RESERVED
0x060 Undefined R RESERVED
0x061 Undefined R RESERVED
0x062 Undefined R RESERVED
0x063 Undefined R RESERVED
0x064 Undefined R RESERVED
0x065 Undefined R RESERVED
0x066 0x02 R/W Timing Calibration Register
0x067 0x01 R/W RESERVED
0x068 Undefined R RESERVED
0x069 Undefined R RESERVED
0x06A 0x00 R/W RESERVED
0x06B 0x20 R/W RESERVED
0x06C-0x1FF Undefined R RESERVED
Digital Down Converter and JESD204B (0x200-0x27F)
0x200 0x10 R/W Digital Down-Converter (DDC) Control
0x201 0x0F R/W JESD204B Control 1
0x202 0x00 R/W JESD204B Control 2
0x203 0x00 R/W JESD204B Device ID (DID)
0x204 0x00 R/W JESD204B Control 3
0x205 Undefined R/W JESD204B and System Status Register
0x206 0xF2 R/W Overrange Threshold 0
0x207 0xAB R/W Overrange Threshold 1
0x208 0x00 R/W Overrange Period
0x209-0x20B 0x00 R/W RESERVED
0x20C 0x00 R/W DDC Configuration Preset Mode
0x20D 0x00 R/W DDC Configuration Preset Select
0x20E-0x20F 0x0000 R/W Rational NCO Reference Divisor
PRESET 0
0x210-0x213 0xC0000000 R/W NCO Frequency (Preset 0)
0x214-0x215 0x0000 R/W NCO Phase (Preset 0)
0x216 0xFF R/W DDC Delay (Preset 0)
0x217 0x00 R/W RESERVED
PRESET 1
0x218-0x21B 0xC0000000 R/W NCO Frequency (Preset 1)
0x21C-0x21D 0x0000 R/W NCO Phase (Preset 1)
0x21E 0xFF R/W DDC Delay (Preset 1)
0x21F 0x00 R/W RESERVED
PRESET 2
0x220-0x223 0xC0000000 R/W NCO Frequency (Preset 2)
0x224-0x225 0x0000 R/W NCO Phase (Preset 2)
0x226 0xFF R/W DDC Delay (Preset 2)
0x227 0x00 R/W RESERVED
PRESET 3
0x228-0x22B 0xC0000000 R/W NCO Frequency (Preset 3)
0x22C-0x22D 0x0000 R/W NCO Phase (Preset 3)
0x22E 0xFF R/W DDC Delay (Preset 3)
0x22F 0x00 R/W RESERVED
PRESET 4
0x230-0x233 0xC0000000 R/W NCO Frequency (Preset 4)
0x234-0x235 0x0000 R/W NCO Phase (Preset 4)
0x236 0xFF R/W DDC Delay (Preset 4)
0x237 0x00 R/W RESERVED
PRESET 5
0x238-0x23B 0xC0000000 R/W NCO Frequency (Preset 5)
0x23C-0x23D 0x0000 R/W NCO Phase (Preset 5)
0x23E 0xFF R/W DDC Delay (Preset 5)
0x23F 0x00 R/W RESERVED
PRESET 6
0x240-0x243 0xC0000000 R/W NCO Frequency (Preset 6)
0x244-0x245 0x0000 R/W NCO Phase (Preset 6)
0x246 0xFF R/W DDC Delay (Preset 6)
0x247 0x00 R/W RESERVED
PRESET 7
0x248-0x24B 0xC0000000 R/W NCO Frequency (Preset 7)
0x24C-0x24D 0x0000 R/W NCO Phase (Preset 7)
0x24E 0xFF R/W DDC Delay (Preset 7)
0x24F-0x251 0x00 R/W RESERVED
0x252-0x27F Undefined R RESERVED
Reserved
0x0280-0x7FFF Undefined R RESERVED
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