Optimum performance of half-bridge gate drivers
cannot be achieved without taking due considerations during circuit board layout.
The following points are emphasized:
- Low-ESR and low-ESL capacitors must be connected
close to the IC between GVDD and GND pins and between BST and SH pins to support
high peak currents being drawn from GVDD and BST during the turn-on of the
external MOSFETs.
- To prevent large voltage transients at the drain
of the top MOSFET, a low-ESR electrolytic capacitor and a good-quality ceramic
capacitor must be connected between the MOSFET drain and ground (GND).
- To avoid large negative transients on the switch
node (SH) pin, the parasitic inductances between the source of the top MOSFET
and the drain of the bottom MOSFET (synchronous rectifier) must be
minimized.
- Grounding considerations:
- The first priority in
designing grounding connections is to confine the high peak currents
that charge and discharge the MOSFET gates to a minimal physical area.
This will decrease the loop inductance and minimize noise issues on the
gate terminals of the MOSFETs. The gate driver must be placed as close
as possible to the MOSFETs.
- The second consideration is the high current path
that includes the bootstrap capacitor, the bootstrap diode, the local
ground referenced bypass capacitor, and the low-side MOSFET body diode.
The bootstrap capacitor is recharged on a cycle-by-cycle basis through
the bootstrap diode from the ground referenced GVDD bypass capacitor.
The recharging occurs in a short time interval and involves high peak
current. Minimizing this loop length and area on the circuit board is
important to ensure reliable operation.