A proper layout is essential for optimum performance of the circuit. In particular, the following guidelines must be observed:

1. C_IN: The loop consisting of input capacitor (C_IN), V_IN pin, and RTN pin carries switching currents. Therefore, the input capacitor must be placed close to the IC, directly across V_IN and RTN pins, and the connections to these two pins must be direct to minimize the loop area. In general, it is not possible to accommodate all of input capacitance near the IC. A good practice is to use a 0.1-μF or 0.47-μF capacitor directly across the V_IN and RTN pins close to the IC, and the remaining bulk capacitor as close as possible (see Figure 10-1).
2. C_VCC and C_BST: The V_CC and bootstrap (BST) bypass capacitors supply switching currents to the high and low side gate drivers. These two capacitors must also be placed as close to the IC as possible, and the connecting trace length and loop area should be minimized (see Figure 10-1).
3. The Feedback trace carries the output voltage information and a small ripple component that is necessary for proper operation of LM25018. Therefore, take care while routing the feedback trace to avoid coupling any noise to this pin. In particular, feedback trace should not run close to magnetic components, or parallel to any other switching trace.
4. SW trace: The SW node switches rapidly between V_IN and GND every cycle and is therefore a possible source of noise. The SW node area should be minimized. In particular, the SW node should not be inadvertently connected to a copper plane or pour.