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ZHCSFK2C July 2012 – September 2016 LM25101

PRODUCTION DATA.

封装选项

机械数据 (封装 | 引脚)

D|8
- MSOI002K
DDA|8
- MPDS092F
DGN|8
- MPDS046G
NGT|8
- MPDS406A
DPR|10
- MPSS046B

散热焊盘机械数据 (封装 | 引脚)

DGN|8
- PPTD274A

订购信息

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

	MIN	MAX	UNIT
VDD to VSS	−0.3	18	V
HB to HS	−0.3	18	V
LI or HI Input	−0.3	V_DD + 0.3	V
LO Output	−0.3	V_DD + 0.3	V
HO Output	V_HS - 0.3	V_HB + 0.3	V
HS to VSS⁽²⁾	–5	100	V
HB to VSS		100	V
Junction temperature, T_J		150	°C
Storage temperature, T_stg	–55	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. For performance limits and associated test conditions, see the Electrical Characteristics tables.

7.2 ESD Ratings

				VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	All pins except 2, 3, and 4	±2000	V
		Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	Pins 2, 3, and 4	±1000
		Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾		±250
		Machine model (MM)		±100

(1) The Human Body Model (HBM) is a 100-pF capacitor discharged through a 1.5-kΩ resistor into each pin.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

			MIN	MAX	UNIT
V_DD	Supply voltage	VDD	9	14	V
V_HS	Voltage	HS	–1	100 – V_DD	V
V_HB	Voltage	HB	V_HS + 8	V_HS + 14	V
	HS slew rate			50	V/ns
T_J	Junction temperature		–40	125	°C

7.4 Thermal Information

THERMAL METRIC⁽¹⁾		LM25101A, LM25101B				LM25101C			UNIT
		D (SOIC)	DDA (SO PowerPAD)	NGT (WSON)	DPR (WSON)	D (SOIC)	DPR (WSON)	DGN (MSOP PowerPAD)
		8 PINS	8 PINS	8 PINS	10 PINS	8 PINS	10 PINS	8 PINS
R_θJA	Junction-to-ambient thermal resistance	108.2	46.1	38.2	37.8	111.5	39.8	54.1	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	50.6	53.5	36.3	35.8	54.2	39.1	55.9	°C/W
R_θJB	Junction-to-board thermal resistance	49.1	13.8	15.2	15.0	52.3	17.1	15.1	°C/W
ψ_JT	Junction-to-top characterization parameter	7.6	4.2	0.3	0.3	9.0	0.4	2.4	°C/W
ψ_JB	Junction-to-board characterization parameter	48.5	13.9	15.4	15.3	51.7	17.3	15.1	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	—	3.9	4.5	4.4	—	6.1	4.6	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

7.5 Electrical Characteristics

Typical values apply for T_J = 25°C only. Minimum and maximum limits apply for T_J= –40°C to 125°C.⁽¹⁾ Unless otherwise specified, V_DD = V_HB = 12 V, V_SS = V_HS = 0 V, No Load on LO or HO.

PARAMETER		TEST CONDITIONS		MIN	TYP	MAX	UNIT
SUPPLY CURRENTS
I_DD	VDD quiescent current	V_LI = V_HI = 0 V			0.25	0.4	mA
I_DDO	VDD operating current	f = 500 kHz			2.0	3	mA
I_HB	Total HB quiescent current	V_LI = V_HI = 0 V			0.06	0.2	mA
I_HBO	Total HB operating current	f = 500 kHz			1.6	3	mA
I_HBS	HB to VSS current (quiescent)	V_HS = V_HB = 100 V			0.1	10	µA
I_HBSO	HB to VSS current (operating)	f = 500 kHz			0.4		mA
INPUT PINS
V_IL	Input voltage threshold	Rising Edge		1.3	1.8	2.3	V
V_IHYS	Input voltage hysteresis				50		mV
R_I	Input pulldown resistance			100	200	400	kΩ
UNDER VOLTAGE PROTECTION
V_DDR	VDD rising threshold			6.0	6.9	7.4	V
V_DDH	VDD threshold hysteresis				0.5		V
V_HBR	HB rising threshold			5.7	6.6	7.1	V
V_HBH	HB threshold hysteresis				0.4		V
BOOT STRAP DIODE
V_DL	Low-current forward voltage	I_VDD-HB = 100 µA			0.52	0.85	V
V_DH	High-current forward voltage	I_VDD-HB = 100 mA			0.8	1	V
RD	Dynamic resistance	I_VDD-HB = 100 mA			1.0	1.65	Ω
LO AND HO GATE DRIVER
V_OL	Low-level output voltage	I_HO = I_LO = 100 mA	A version		0.12	0.25	V
			B version		0.16	0.4
			C version		0.28	0.65
V_OH	High-level output voltage	I_HO = I_LO = 100 mA V_OH = V_DD – V_LO or V_OH = V_HB – V_HO	A version		0.24	0.45	V
			B version		0.28	0.60
			C version		0.60	1.10
I_OHL	Peak pullup current	HO, V_LO = 0 V	A version		3		A
			B version		2
			C version		1
I_OLL	Peak pulldown current	HO, V_LO = 12 V	A version		3		A
			B version		2
			C version		1

7.6 Switching Characteristics

PARAMETER		TEST CONDITIONS		TYP	MAX	UNIT
t_LPHL	LO turnoff propagation delay	LI falling to LO falling		22	56	ns
t_LPLH	LO turnon propagation delay	LI rising to LO rising		26	56	ns
t_HPHL	HO turnoff propagation delay	HI falling to HO falling		22	56	ns
t_HPLH	LO turnon propagation delay	HI rising to HO rising		26	56	ns
t_MON	Delay matching	LO ON and HO OFF		4	10	ns
t_MOFF	Delay matching	LO OFF and HO ON		4	10	ns
t_RC, t_FC	Either output rise and fall time	C_L = 1000 pF		8		ns
t_R	Output rise time (3 V to 9 V)	C_L = 0.1 µF	A version	430		ns
			B version	570
			C version	990
t_F	Output fall time (3 V to 9 V)	C_L = 0.1 µF	A version	260		ns
			B version	430
			C version	715
t_PW	Minimum input pulse duration that changes the output			50		ns
t_BS	Bootstrap diode reverse recovery time	I_F = 100 mA, I_R = 100 mA		37		ns

(1) Minimum and maximum limits are 100% production tested at 25°C. Limits over the operating temperature range are specified through correlation using Statistical Quality Control (SQC) methods. Limits are used to calculate Average Outgoing Quality Level (AOQL).

(2) In the application the HS node is clamped by the body diode of the external lower N-MOSFET, therefore the HS node will generally not exceed –1 V. However, in some applications, board resistance and inductance may result in the HS node exceeding this stated voltage transiently. If negative transients occur, the HS voltage must never be more negative than V_DD – 15 V. For example, if V_DD = 10 V, the negative transients at HS must not exceed –5 V.