R_COMP, C_COMP and C_HF configure the error amplifier gain characteristics to accomplish a stable voltage loop gain. One advantage of current mode control is the ability to close the loop with only two feedback components, R_COMP and C_COMP. The voltage loop gain is the product of the modulator gain and the error amplifier gain. For the 5-V output design example, the modulator is treated as an ideal voltage-to-current converter. The DC modulator gain of the LM25116 can be modeled with Equation 33.

The dominant low frequency pole of the modulator is determined by the load resistance (R_LOAD) and output capacitance (C_OUT). The corner frequency of this pole is calculated with Equation 34.

For R_LOAD = 5 V / 7 A = 0.714 Ω and C_OUT = 320 µF (effective) then f_P(MOD) = 700 Hz

DC Gain_(MOD) = 0.714 Ω / (10 × 10 mΩ) = 7.14 = 17 dB

For the 5-V design example, the modulator gain versus frequency characteristic was measured as shown in Figure 7-3.

Figure 7-3 Modulator Gain and Phase

Components R_COMP and C_COMP configure the error amplifier as a type II configuration. The DC gain of the amplifier is 80 dB which has a pole at low frequency and a zero at f_ZEA = 1 / (2π x R_COMP × C_COMP). The error amplifier zero cancels the modulator pole leaving a single pole response at the crossover frequency of the voltage loop. A single pole response at the crossover frequency yields a very stable loop with 90° of phase margin. For the design example, a target loop bandwidth (crossover frequency) of one-tenth the switching frequency or 25 kHz was selected. The compensation network zero (f_ZEA) must be selected at least an order of magnitude less than the target crossover frequency. This constrains the product of R_COMP and C_COMP for a desired compensation network zero 1 / (2π × R_COMP × C_COMP) to be 2.5 kHz. Increasing R_COMP, while proportionally decreasing C_COMP, increases the error amp gain. Conversely, decreasing R_COMP while proportionally increasing C_COMP, decreases the error amp gain. For the design example, C_COMP was selected as 3300 pF and R_COMP was selected as 18 kΩ. These values configure the compensation network zero at 2.7 kHz. The error amp gain at frequencies greater than f_ZEA is: R_COMP / R_FB2, which is approximately 4.8 (13.6 dB).

Figure 7-4 Error Amplifier Gain and Phase

The overall voltage loop gain can be predicted as the sum (in dB) of the modulator gain and the error amp gain.

Figure 7-5 Overall Voltage Loop Gain and Phase

If a network analyzer is available, the modulator gain can be measured and the error amplifier gain can be configured for the desired loop transfer function. If a network analyzer is not available, the error amplifier compensation components can be designed with the guidelines given. Step load transient tests can be performed to verify acceptable performance. The step load goal is minimum overshoot with a damped response. C_HF can be added to the compensation network to decrease noise susceptibility of the error amplifier. The value of C_HF must be sufficiently small because the addition of this capacitor adds a pole in the error amplifier transfer function. This pole must be well beyond the loop crossover frequency. A good approximation of the location of the pole added by C_HF is: f_P2 = f_ZEA × C_COMP / C_HF. The value of C_HF was selected as 100 pF for the design example.