ZHCSGG8F July 2011 – March 2018 LM25118
PRODUCTION DATA.
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
VIN SUPPLY | |||||||
IBIAS | VIN operating current | VCCX = 0 V | 4.5 | 5.5 | mA | ||
IBIASX | VIN operating current | VCCX = 5 V | 1 | 1.85 | mA | ||
ISTDBY | VIN shutdown current | EN = 0 V | 1 | 10 | µA | ||
VCC REGULATOR | |||||||
VCC(REG) | VCC regulation | VCCX = 0 V | 6.8 | 7 | 7.2 | V | |
VCC(REG) | VCC regulation | VCCX = 0 V, VIN = 6 V | 5 | 5.25 | 5.5 | V | |
VCC sourcing current limit | VCC = 0 | 21 | 35 | mA | |||
VCCX switch threshold | VCCX rising | 3.68 | 3.85 | 4.02 | V | ||
VCCX switch hysterisis | 0.2 | V | |||||
VCCX switch RDS(ON) | ICCX = 10 mA | 5 | 12 | Ω | |||
VCCX switch leakage | VCCX = 0 V | 0.5 | 1 | µA | |||
VCCCX pulldown resistance | VCCX = 3 V | 70 | kΩ | ||||
VCC undervoltage lockout voltage | VCC rising | 3.52 | 3.7 | 3.86 | V | ||
VCC undervoltage hysterisis | 0.21 | V | |||||
HB DC bias current | HB-HS = 15 V | 205 | 260 | µA | |||
VC LDO mode turnoff | 10 | V | |||||
EN INPUT | |||||||
VEN(OFF) | EN input low threshold | VEN falling | 0.5 | V | |||
VEN(ON) | EN input high threshold | VEN rising | 3 | V | |||
EN input bias current | VEN = 3 V | –1 | 1 | µA | |||
EN input bias current | VEN = 0.5 V | –1 | 1 | µA | |||
EN input bias current | VEN = 42 V | 50 | µA | ||||
UVLO THRESHOLDS | |||||||
UVLO | UVLO standby threshold | UVLO Rising | 1.191 | 1.231 | 1.271 | V | |
ΔUVLO | UVLO threshold hysteresis | 0.105 | V | ||||
UVLO pullup current source | UVLO = 0 V | 5 | µA | ||||
UVLO pulldown RDS(ON) | 100 | 200 | Ω | ||||
SOFT START | |||||||
SS current source | SS = 0 V | 7.5 | 10.5 | 13.5 | µA | ||
SS to FB offset | FB = 1.23 V | 150 | mV | ||||
SS output low voltage | Sinking 100 µA, UVLO = 0 V | 7 | mV | ||||
ERROR AMPLIFIER | |||||||
VREF | FB reference voltage | Measured at FB pin,
FB = COMP |
1.212 | 1.23 | 1.248 | V | |
FB input bias current | FB = 2 V | 20 | 200 | nA | |||
COMP sink/source current | 3 | mA | |||||
AOL | DC gain | 80 | dB | ||||
fBW | Unity bain bandwidth | 3 | MHz | ||||
PWM COMPARATORS | |||||||
tHO(OFF) | Forced HO off-time | 305 | 400 | 495 | ns | ||
TON(MIN) | Minimum HO on-time | 70 | ns | ||||
COMP to comparator offset | 200 | mV | |||||
OSCILLATOR (RT PIN) | |||||||
fSW1 | Frequency 1 | RT = 29.11 kΩ | 178 | 200 | 224 | kHz | |
fSW2 | Frequency 2 | RT = 9.525 kΩ | 450 | 515 | 575 | kHz | |
SYNC | |||||||
Sync threshold falling | 1.3 | V | |||||
CURRENT LIMIT | |||||||
VCS(TH) | Cycle-by-cycle sense voltage threshold (CS-CSG) | RAMP = 0 buck mode | –103 | –125 | –147 | mV | |
VCS(THX) | Cycle-by-cycle sense voltage threshold (CS-CSG) | RAMP = 0 buck-boost mode | –218 | –255 | –300 | mV | |
CS bias current | CS = 0 V | 45 | 60 | µA | |||
CSG bias current | CSG = 0 V | 45 | 60 | µA | |||
Current limit fault timer | 256 | cycles | |||||
RAMP GENERATOR | |||||||
IR2 | RAMP current 2 | VIN = 12 V, VOUT = 12 V | 95 | 115 | 135 | µA | |
IR3 | RAMP current 3 | VIN = 5 V, VOUT = 12 V | 65 | 80 | 95 | µA | |
VOUT bias current | VOUT = 42 V | 245 | µA | ||||
LOW-SIDE (LO) GATE DRIVER | |||||||
VOLL | LO low-state output voltage | ILO = 100 mA | 0.14 | 0.23 | V | ||
VOHL | LO high-state output voltage | ILO = –100 mA
VOHL = VCC-VLO |
0.25 | V | |||
LO rise time | C-load = 1 nF, VCC = 8 V | 16 | ns | ||||
LO fall time | C-load = 1 nF, VCC = 8 V | 14 | ns | ||||
IOHL | Peak LO source current | VLO = 0 V, VCC = 8 V | 2.2 | A | |||
IOLL | Peak LO sink current | VLO = VCC = 8 V | 2.7 | A | |||
HIGH-SIDE (HO) GATE DRIVER | |||||||
VOLH | HO low-state output voltage | IHO = 100 mA | 0.135 | 0.21 | V | ||
VOHH | HO high-state output voltage | IHO = –100 mA,
VOHH = VHB-VOH |
0.25 | V | |||
HO rise time | C-load = 1 nF, VCC = 8 V | 14 | ns | ||||
HO fall time | C-load = 1 nF, VCC = 8 V | 12 | ns | ||||
IOHH | Peak HO source current | VHO = 0 V, VCC = 8 V | 2.2 | A | |||
IOLH | Peak HO sink current | VHO = VCC = 8 V | 3.5 | A | |||
HB-HS undervoltage lockout | 3 | V | |||||
BUCK-BOOST CHARACTERISTICS(3) | |||||||
Buck-boost mode | Buck duty cycle | 69% | 75% | 80% | |||
THERMAL | |||||||
TSD | Thermal shutdown junction temperature | 165 | °C | ||||
ΔTSD | Thermal shutdown hysterisis | 25 | °C |